公开(公告)号：US20200381346A1

公开(公告)日：2020-12-03

申请号：US16995014

申请日：2020-08-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ming-Fa Chen ,  Chen-Hua Yu

IPC: H01L23/498 ,  G01R1/04 ,  H01L21/48 ,  H01L21/683 ,  H01L23/32 ,  H01L23/00 ,  H01L25/065 ,  H05K1/14 ,  H05K3/46 ,  H05K7/10

Abstract: A method includes forming a plurality of dielectric layers, forming a plurality of redistribution lines in the plurality of dielectric layers, etching the plurality of dielectric layers to form an opening, filling the opening to form a through-dielectric via penetrating through the plurality of dielectric layers, forming a dielectric layer over the through-dielectric via and the plurality of dielectric layers, forming a plurality of bond pads in the dielectric layer, bonding a device die to the dielectric layer and a first portion of the plurality of bond pads through hybrid bonding, and bonding a die stack to through-silicon vias in the device die.

公开(公告)号：US20200343223A1

公开(公告)日：2020-10-29

申请号：US16398138

申请日：2019-04-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsien-Wei Chen ,  Ming-Fa Chen ,  Sung-Feng Yeh ,  Chao-Wen Shih

IPC: H01L25/065 ,  H01L23/28 ,  H01L23/498 ,  H01L23/538 ,  H01L23/00

Abstract: A package structure includes a first semiconductor die, a second semiconductor die, an insulating encapsulant and a redistribution layer. The first semiconductor die has first conductive posts and a first protection layer laterally surrounding the first conductive posts. The second semiconductor die is embedded in the first protection layer and surrounded by the first conductive posts of the first semiconductor die, wherein the second semiconductor die includes second conductive posts. The insulating encapsulant is encapsulating the first semiconductor die and the second semiconductor die. The redistribution layer is disposed on the insulating encapsulant and connected with the first conductive posts and the second conductive posts, wherein the first semiconductor die is electrically connected with the second semiconductor die through the first conductive posts, the redistribution layer and the second conductive posts.

公开(公告)号：US20200343218A1

公开(公告)日：2020-10-29

申请号：US16398159

申请日：2019-04-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Chia Hu ,  Ming-Fa Chen ,  Sung-Feng Yeh

IPC: H01L25/065 ,  H01L25/00 ,  H01L23/00 ,  H01L21/683

Abstract: Provided are integrated circuit packages and methods of forming the same. An integrated circuit package includes an integrated circuit structure, a first die stack and a dummy die. The first die stack includes a plurality of first die structures and is bonded to the integrated circuit structure at a first side of the first die stack. The dummy die includes a plurality of through substrate vias, is located aside the first die stack and is electrically connected to the integrated circuit structure at the first side of the first die stack. In some embodiments, the height of the through substrate vias of the dummy die is the same as the height of the first die stack.

公开(公告)号：US09633917B2

公开(公告)日：2017-04-25

申请号：US14830740

申请日：2015-08-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wen-Ching Tsai ,  Ming-Fa Chen ,  Chen-Hua Yu

IPC: H01L25/065 ,  H01L21/66 ,  H01L23/31 ,  H01L23/538 ,  H01L23/00 ,  H01L25/00 ,  H01L21/56 ,  H01L21/82

CPC classification number: H01L22/32 ,  H01L21/563 ,  H01L21/82 ,  H01L22/14 ,  H01L22/20 ,  H01L23/3171 ,  H01L23/538 ,  H01L23/5384 ,  H01L24/03 ,  H01L24/09 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/0236 ,  H01L2224/02372 ,  H01L2224/08235 ,  H01L2924/37001

Abstract: Provided is a three dimensional integrated circuit structure including a first die, a through substrate via and a connector. The first die is bonded to a second die with a first dielectric layer of the first die and a second dielectric layer of the second die, wherein a first passivation layer is between the first dielectric layer and a first substrate of the first die, and a first test pad is embedded in the first passivation layer. The through substrate via penetrates through the first die and is electrically connected to the second die. The connector is electrically connected to the first die and the second die through the through substrate via.

公开(公告)号：US12266612B2

公开(公告)日：2025-04-01

申请号：US18525966

申请日：2023-12-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsien-Pin Hu ,  Chen-Hua Yu ,  Ming-Fa Chen ,  Jing-Cheng Lin ,  Jiun Ren Lai ,  Yung-Chi Lin

IPC: H01L21/683 ,  H01L21/56 ,  H01L23/00 ,  H01L23/14 ,  H01L23/31 ,  H01L23/498 ,  H01L23/538 ,  H01L25/065

Abstract: A device includes an interposer, which includes a substrate having a top surface. An interconnect structure is formed over the top surface of the substrate, wherein the interconnect structure includes at least one dielectric layer, and metal features in the at least one dielectric layer. A plurality of through-substrate vias (TSVs) is in the substrate and electrically coupled to the interconnect structure. A first die is over and bonded onto the interposer. A second die is bonded onto the interposer, wherein the second die is under the interconnect structure.

公开(公告)号：US12249580B2

公开(公告)日：2025-03-11

申请号：US18358530

申请日：2023-07-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsien-Wei Chen ,  Ying-Ju Chen ,  Ming-Fa Chen

IPC: H01L23/00 ,  H01L21/74 ,  H01L21/78 ,  H01L23/31 ,  H01L23/525 ,  H01L23/544 ,  H01L23/58

Abstract: A method of forming a semiconductor device includes: forming first electrical components in a substrate in a first device region of the semiconductor device; forming a first interconnect structure over and electrically coupled to the first electrical components; forming a first passivation layer over the first interconnect structure, the first passivation layer extending from the first device region to a scribe line region adjacent to the first device region; after forming the first passivation layer, removing the first passivation layer from the scribe line region while keeping a remaining portion of the first passivation layer in the first device region; and dicing along the scribe line region after removing the first passivation layer.

公开(公告)号：US12218097B2

公开(公告)日：2025-02-04

申请号：US18364310

申请日：2023-08-02

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsien-Wei Chen ,  Ying-Ju Chen ,  Ming-Fa Chen

IPC: H01L23/544 ,  H01L21/304 ,  H01L21/683 ,  H01L21/768 ,  H01L23/00 ,  H01L23/48 ,  H01L25/00 ,  H01L25/065

Abstract: A method includes placing a first package component. The first package component includes a first alignment mark and a first dummy alignment mark. A second package component is aligned to the first package component. The second package component includes a second alignment mark and a second dummy alignment mark. The aligning is performed using the first alignment mark for positioning the first package component, and using the second alignment mark for position the second package component. The second package component is bonded to the first package component to form a package, with the first alignment mark being bonded to the second dummy alignment mark.

公开(公告)号：US20240387467A1

公开(公告)日：2024-11-21

申请号：US18786470

申请日：2024-07-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsien-Wei Chen ,  Ming-Fa Chen

IPC: H01L25/065 ,  H01L21/48 ,  H01L21/56 ,  H01L21/683 ,  H01L21/768 ,  H01L23/00 ,  H01L23/31 ,  H01L23/48 ,  H01L23/538 ,  H01L23/544 ,  H01L25/00 ,  H01L25/10

Abstract: A semiconductor package includes a first die, a second die, an encapsulating material, and a redistribution structure. The second die is disposed over the first die and includes a plurality of bonding pads bonded to the first die, a plurality of through vias extending through a substrate of the second die and a plurality of alignment marks, wherein a pitch between adjacent two of the plurality of alignment marks is different from a pitch between adjacent two of the plurality of through vias. The encapsulating material is disposed over the first die and at least laterally encapsulating the second die. The redistribution structure is disposed over the second die and the encapsulating material and electrically connected to the plurality of through vias.

公开(公告)号：US20240379521A1

公开(公告)日：2024-11-14

申请号：US18783669

申请日：2024-07-25

Applicant: Taiwan Semiconductor Manufacturing Co, Ltd

Inventor： Ming-Fa Chen ,  Chin-Shyh Wang ,  Chao-Wen Shih

IPC: H01L23/498 ,  H01L21/762 ,  H01L21/768

Abstract: A method includes etching a substrate to form an opening, depositing a first dielectric liner extending into the opening, and depositing a second dielectric liner over the first dielectric liner. The second dielectric liner extends into the opening. A conductive material is filled into the opening. The method further includes performing a first planarization process to planarize the conductive material so that a portion of the conductive material in the opening forms a through-via, performing a backside grinding process on the substrate until the through-via is revealed from a backside of the substrate, and forming a conductive feature on the backside of the substrate. The conductive feature is electrically connected to the through-via.

公开(公告)号：US20240379439A1

公开(公告)日：2024-11-14

申请号：US18781604

申请日：2024-07-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ming-Fa Chen ,  Tzuan-Horng Liu ,  Chao-Wen Shih

IPC: H01L21/768 ,  H01L21/3065 ,  H01L23/00 ,  H01L25/00 ,  H01L25/065

Abstract: An embodiment is a method including forming a first interconnect structure over a first substrate, the first interconnect structure comprising dielectric layers and metallization patterns therein, patterning the first interconnect structure to form a first opening, coating the first opening with a barrier layer, etching a second opening through the barrier layer and the exposed portion of the first substrate, depositing a liner in the first opening and the second opening, filling the first opening and the second opening with a conductive material, and thinning the first substrate to expose a portion of the conductive material in the second opening, the conductive material extending through the first interconnect structure and the first substrate forming a through substrate via.