公开(公告)号：US07456687B2

公开(公告)日：2008-11-25

申请号：US11790982

申请日：2007-04-30

Applicant: Akira Seino ,  Hiroaki Maeda ,  Takashi Ono ,  Yousuke Okazaki

Inventor： Akira Seino ,  Hiroaki Maeda ,  Takashi Ono ,  Yousuke Okazaki

IPC: H03F3/68

CPC classification number: H03F1/0288 ,  H03F1/52 ,  H03F2200/207 ,  H03F2200/465 ,  H03F2200/471

Abstract: The present invention provides an amplifier unit including a carrier amplifier biased for Class A or Class AB operation; a peak amplifier biased for Class B or Class C operation, wherein an input signal is input to the carrier amplifier and the peak amplifier, and wherein output signals from the carrier amplifier and the peak amplifier are synthesized to output therefrom; a comparator configured to compare a gate bias voltage of a transistor device in the peak amplifier with a predetermined threshold voltage and output a first output signal; and a failure detection circuit configured to output a second output signal indicating presence or absence of failure, based on the first output signal received from the comparator.

Abstract translation: 本发明提供一种放大器单元，其包括偏置用于A类或AB类操作的载波放大器; 偏置用于B类或C类工作的峰值放大器，其中输入信号被输入到载波放大器和峰值放大器，并且其中来自载波放大器和峰值放大器的输出信号被合成以从其输出; 比较器，用于将所述峰值放大器中的晶体管器件的栅极偏置电压与预定阈值电压进行比较，并输出第一输出信号; 以及故障检测电路，被配置为基于从所述比较器接收到的所述第一输出信号，输出指示故障有无的第二输出信号。

公开(公告)号：US20080231877A1

公开(公告)日：2008-09-25

申请号：US12049448

申请日：2008-03-17

Applicant: Takashi Ono

Inventor： Takashi Ono

IPC: H04N1/46

CPC classification number: H04N1/58 ,  H04N1/484

Abstract: This invention solves the problem of color misalignment upon reading a color image. An image reading apparatus according to this invention reads an image by scanning a scanning unit which mounts a reading sensor which reads light beams which are emitted by three light sources, which emit light beams of three primary colors, and reflected by an original document. The image reading apparatus conveys the original document by ⅓ of the reading width of the reading sensor in the conveyance direction of the original document every time the image is read. The image is read by switching between the three light sources so that each pixel of the image is read with the light beams from them.

Abstract translation: 本发明解决了在读取彩色图像时颜色不对准的问题。 根据本发明的图像读取装置通过扫描安装读取传感器的扫描单元来读取图像，该读取传感器读取由三个光源发射并由原始文档反射的三个光源发射的光束。 每次读取图像时，图像读取装置将原稿以原稿的传送方向传送读取传感器的读取宽度的1/3。 通过在三个光源之间切换来读取图像，使得图像的每个像素都被来自它们的光束读取。

公开(公告)号：US20070285711A1

公开(公告)日：2007-12-13

申请号：US11758827

申请日：2007-06-06

Applicant: Takashi Ono

Inventor： Takashi Ono

IPC: G06F3/12

CPC classification number: G06F3/1288

Abstract: A printing system that adopts an SBC system in which a load at a server is alleviated when executing printing to enable printing to be performed smoothly. In the printing system, a client terminal, a server, and an image forming apparatus are connected to each other through a network. The client terminal specifies data among stored data in the server and sends a print execution request to the server. The server receives the print execution request, creates print-related information relating to the specified data, and sends it to the client terminal. The client terminal judges whether or not print data generation processing with respect to the specified data is possible at the client terminal based on the print-related information, and send the judgment result to the server. The server allocates the print data generation processing to either the server or the client terminal based on the judgment result.

Abstract translation: 一种采用SBC系统的打印系统，其中在执行打印时减轻了服务器的负载，使打印顺利进行。 在打印系统中，客户终端，服务器和图像形成装置通过网络彼此连接。 客户终端指定服务器中存储的数据之间的数据，并向服务器发送打印执行请求。 服务器接收打印执行请求，创建与指定数据相关的打印相关信息，并发送给客户端。 客户终端基于打印相关信息判断在客户终端是否可以进行关于指定数据的打印数据生成处理，并将判断结果发送给服务器。 服务器根据判断结果将打印数据生成处理分配给服务器或客户终端。

公开(公告)号：US20070146953A1

公开(公告)日：2007-06-28

申请号：US11642790

申请日：2006-12-21

Applicant: Takashi Ono

Inventor： Takashi Ono

IPC: H02H3/00

CPC classification number: H03K17/063 ,  H01L27/0255 ,  H03K17/122 ,  H03K17/6872 ,  H03K2217/0018

Abstract: In a conventional switch circuit capable of bidirectional conductivity, there is the problem that latch-up occurs in a parasitic thyristor included in a transistor having a switching function. Therefore it is an object of the present invention to provide a switch circuit capable of bidirectional conductivity while suppressing the occurrence of latch-up due to a parasitic thyristor. The present invention provides a switch circuit that includes diodes connected in parallel with each of a MOS transistor having the switching function and parasitic diodes present at the source and the drain of the MOS transistor.

Abstract translation: 在具有双向电导率的常规开关电路中，存在在具有开关功能的晶体管中包括的寄生晶闸管中发生闩锁的问题。 因此，本发明的目的是提供一种能够在抑制由寄生晶闸管引起的闩锁的发生的同时具有双向电导率的开关电路。 本发明提供一种开关电路，其包括与具有开关功能的MOS晶体管和MOS晶体管的源极和漏极存在的寄生二极管并联连接的二极管。

公开(公告)号：US07211878B2

公开(公告)日：2007-05-01

申请号：US10739215

申请日：2003-12-19

Applicant: Takashi Ono

Inventor： Takashi Ono

IPC: H01L23/58

CPC classification number: G11C16/0475 ,  H01L29/7923

Abstract: A memory cell structure and control of the memory operation are simplified, and the cost of production is decreased, by way of a semiconductor nonvolatile memory having a transistor including a gate electrode provided on a p-type semiconductor substrate via a gate insulating film, and a source region and a drain region, which are a pair of n-type impurity diffusion regions in the surface layer region of the semiconductor substrate at positions sandwiching the gate electrodes therebetween. A first resistance-varying portion and a second resistance-varying portion are sandwiched by the source region, drain region and channel-forming region. The n-type impurity concentration in the resistance-varying portions is lower than in the source and drain regions.

Abstract translation: 简化了存储器单元结构和存储器操作的控制，并且通过具有晶体管的半导体非易失性存储器来降低生产成本，所述半导体非易失性存储器具有通过栅极绝缘膜设置在p型半导体衬底上的栅电极，以及 源极区域和漏极区域，它们是在半导体衬底的表面层区域中的夹着栅电极的位置处的一对n型杂质扩散区域。 第一电阻变化部分和第二电阻变化部分被源极区域，漏极区域和沟道形成区域夹在中间。 电阻变化部分中的n型杂质浓度低于源区和漏区。

公开(公告)号：US20060283413A1

公开(公告)日：2006-12-21

申请号：US11446143

申请日：2006-06-05

Applicant: Shigeru Kawakami ,  Takashi Ono

Inventor： Shigeru Kawakami ,  Takashi Ono

IPC: F01L1/34

CPC classification number: F01L13/0026 ,  F01L1/143 ,  F01L2013/0073 ,  F01L2820/032 ,  Y10T74/18576

Abstract: A rotary shaft is formed with an external screw thread; a movable nut is engaged with the rotary shaft, and arranged to move axially in accordance with rotation of the rotary shaft; and a link member is swingablly connected with the movable nut to transmit motion from the movable nut. The link member includes first and second side portions and a connecting portion connecting the first and second side portions and forming a depressed portion in which the rotary shaft is received when the link member is in a predetermined leaning posture.

Abstract translation: 旋转轴形成有外螺纹; 可动螺母与旋转轴接合并且被设置为根据旋转轴的旋转轴向移动; 并且连杆构件与可动螺母摆动地连接以从可动螺母传递运动。 连杆构件包括第一和第二侧部以及连接第一和第二侧部的连接部分，并且当连杆构件处于预定的倾斜姿势时形成凹部，在该凹部中容纳旋转轴。

公开(公告)号：US20060094209A1

公开(公告)日：2006-05-04

申请号：US11262770

申请日：2005-11-01

Applicant: Kazuma Sekiya ,  Takashi Ono

Inventor： Kazuma Sekiya ,  Takashi Ono

IPC: H01L21/78

CPC classification number: H01L21/78 ,  G03F7/265 ,  G03F7/36 ,  H01L21/3086

Abstract: To divide into individual devices efficiently in dicing a wafer without causing quality of the devices to lower, a wafer processing method includes steps of coating a rear surface of the wafer with a resist film, exposing and sensitizing portions of the resist film other than regions corresponding to the streets; and supplying a silylation agent onto a surface of the resist film and silylating the resist film in a sensitized region. In an etching unit, an oxygen- or chlorine-containing gas is plasmatized and supplied to a rear surface of the wafer coated with a silylated resist film, and the resist film in an unsilylated regions corresponding to the streets is ashed and removed. A stable fluoride gas is plasmatized and supplied to the rear surface of the wafer, and the resist film in the regions corresponding to the streets is etch-removed to divide the wafer W into individual devices.

Abstract translation: 为了在不导致设备质量降低的情况下有效地划分为单个设备，晶片处理方法包括以下步骤：用抗蚀剂膜涂覆晶片的后表面，对除了对应的区域之外的抗蚀剂膜的部分进行曝光和增感 到街上 并将硅烷化剂供应到抗蚀剂膜的表面上，并使敏化区域中的抗蚀剂膜甲硅烷基化。 在蚀刻单元中，将含氧气或含氯气体等离子化并供给到涂覆有甲硅烷基化抗蚀剂膜的晶片的后表面，并且对应于街道的未溶胶化区域中的抗蚀剂膜被去灰和除去。 将稳定的氟化物气体等离子化并提供给晶片的后表面，并且蚀刻除去与街道对应的区域中的抗蚀剂膜，以将晶片W分成单独的器件。

公开(公告)号：US20060008982A1

公开(公告)日：2006-01-12

申请号：US11060297

申请日：2005-02-18

Applicant: Takashi Ono

Inventor： Takashi Ono

IPC: H01L21/336

CPC classification number: G11C16/0475 ,  G11C11/5671 ,  G11C16/0491 ,  H01L21/28282 ,  H01L29/66833 ,  H01L29/7923 ,  Y10S438/91

Abstract: In one example, a nonvolatile semiconductor memory includes a transistor, one or two resistance-change portions, and one or two charge accumulation portions. The transistor has a control electrode, first main electrode region, and second main electrode region. If two resistance-change portions are provided, one of them is provided in the surface region of a substrate between the first main electrode region and a channel formation region opposing the control electrode, and the other is provided in the surface region of the substrate between the second main electrode region and the channel formation region. Each resistance-change portion is of a second conductivity type having impurity concentration lower than that of the first and second main electrode regions. The charge accumulation portions are provided on the associated resistance-change portions. Each charge accumulation portion has an insulating layer, and is capable of accumulating charge. It should be assumed that information is recorded in such nonvolatile semiconductor memory in which information has been erased in advance by charge accumulation. When the first conductivity type is the p type and the second conductivity type is the n type, an information recording method includes applying a high positive voltage to one of the main electrode regions, setting the other main electrode region to ground voltage, and applying a positive voltage to the control electrode so as to cause weak inversion of the channel formation region.

Abstract translation: 在一个示例中，非易失性半导体存储器包括晶体管，一个或两个电阻变化部分以及一个或两个电荷累积部分。 晶体管具有控制电极，第一主电极区域和第二主电极区域。 如果设置两个电阻变化部分，则在第一主电极区域和与控制电极相对的沟道形成区域之间的衬底的表面区域中设置两个电阻变化部分，另一个设置在衬底的表面区域中 第二主电极区域和沟道形成区域。 每个电阻变化部分具有杂质浓度低于第一和第二主电极区域的第二导电类型。 电荷累积部分设置在相关联的电阻变化部分上。 每个电荷累积部分具有绝缘层，并且能够积聚电荷。 应该假设信息被记录在这样的非易失性半导体存储器中，其中已经通过电荷累积预先擦除了信息。 当第一导电类型是p型并且第二导电类型是n型时，信息记录方法包括向主电极区域之一施加高正电压，将另一主电极区域设置为接地电压，并施加 对控制电极施加正电压，从而引起通道形成区域的弱反转。

公开(公告)号：US20050282630A1

公开(公告)日：2005-12-22

申请号：US11172827

申请日：2005-07-05

Applicant: Tetsuya Kaku ,  Yuichiro Mine ,  Takashi Ono ,  Norio Haga ,  Makoto Osaki ,  Takayuki Yamaguchi ,  Norihiro Sekine ,  Ryoya Yui ,  Saori Nishikawa ,  Tetsuya Sugimoto ,  Shigeru Yoshida ,  Manabu Nakatani ,  Masumi Uchida

Inventor： Tetsuya Kaku ,  Yuichiro Mine ,  Takashi Ono ,  Norio Haga ,  Makoto Osaki ,  Takayuki Yamaguchi ,  Norihiro Sekine ,  Ryoya Yui ,  Saori Nishikawa ,  Tetsuya Sugimoto ,  Shigeru Yoshida ,  Manabu Nakatani ,  Masumi Uchida

IPC: A63F9/24 ,  A63F13/00 ,  G06T13/20 ,  G06T13/40 ,  G06T13/60 ,  G06T15/00 ,  G06T15/04 ,  G06T19/00

CPC classification number: A63F13/57 ,  A63F13/10 ,  A63F13/52 ,  A63F13/56 ,  A63F13/833 ,  A63F2300/63 ,  A63F2300/64 ,  A63F2300/66 ,  A63F2300/6607 ,  A63F2300/6661 ,  A63F2300/6692 ,  A63F2300/8029 ,  G06T13/20 ,  G06T13/40

Abstract: This image processing device for games is a device whereby a prescribed number of models (characters) are setup in virtual space, these models are controlled such that they move in prescribed directions in the virtual space, and images of this virtual space from a virtual viewpoint are displayed on means for display. In order to display the movement of the models that are arranged in virtual space more realistically, in one construction thereof, this device is provided with means for image processing that apply virtual centripetal force to the models. Furthermore, in order to display the movement of the models more realistically and to heighten the dramatic effect, in one construction thereof, this device is equipped with means for processing residual image presentation in order to represent the track of movement of a model as residual images. This means for processing is equipped with means for storage that store without modification motion data of the model prior to the current motion and with means for display control that display this stored data together with the current motion data.

Abstract translation: 该游戏用图像处理装置是在虚拟空间中设定规定数量的模型（文字）的装置，这些模型被控制为使得它们在虚拟空间中以规定的方向移动，并且虚拟视点的该虚拟空间的图像 显示在显示器上。 为了更真实地显示在虚拟空间中布置的模型的移动，在其一个构造中，该装置具有将虚拟向心力应用于模型的图像处理装置。 此外，为了更逼真地显示模型的移动并提高戏剧效果，在其一个构造中，该装置配备有用于处理残余图像呈现的装置，以便将模型的移动轨迹表示为残差图像 。 这意味着处理装备有存储装置，在没有修改当前运动之前的模型的运动数据的情况下，以及显示控制装置以及当前的运动数据显示该存储的数据。

公开(公告)号：US20050247969A1

公开(公告)日：2005-11-10

申请号：US10837700

申请日：2004-05-04

Applicant: Takashi Ono ,  Shoji Kitazawa ,  Teruhiro Harada

Inventor： Takashi Ono ,  Shoji Kitazawa ,  Teruhiro Harada

IPC: H01L21/8239 ,  H01L27/105 ,  H01L27/115 ,  H01L29/76 ,  H01L29/792

CPC classification number: H01L29/7923 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/115 ,  H01L29/685

Abstract: A nonvolatile semiconductor memory device includes a plurality of memory cells. A couple of bits of data can be stored in the memory cell, the stored data being controlled according to resistance values of first and second variable resistance regions. One of the plurality of memory cells shares its first diffusion layer with an adjacent memory cell and shares its second diffusion layer with another adjacent memory cell. The first diffusion layers of the plurality of memory cells are coupled to each other with a first conductive line extending in a first direction. The second diffusion layers of the plurality of memory cells are coupled to each other with a second conductive line extending in the first direction. The gate electrodes of the plurality of memory cells are coupled to each other with a third conductive line extending in a second direction, which is orthogonal to the first direction.

Abstract translation: 非易失性半导体存储器件包括多个存储单元。 可以将数位数据存储在存储单元中，存储的数据根据​​第一和第二可变电阻区域的电阻值进行控制。 多个存储单元中的一个与相邻存储单元共享其第一扩散层，并且与另一个相邻的存储单元共享其第二扩散层。 多个存储单元的第一扩散层通过沿第一方向延伸的第一导线彼此耦合。 多个存储单元的第二扩散层通过沿第一方向延伸的第二导线相互耦合。 多个存储单元的栅电极通过与第一方向正交的第二方向延伸的第三导线彼此耦合。