公开(公告)号：US08536919B1

公开(公告)日：2013-09-17

申请号：US12909781

申请日：2010-10-21

申请人： Allen Chan ,  Wilson Wong

发明人： Allen Chan ,  Wilson Wong

IPC分类号： H03K3/00

CPC分类号： H03K3/0375 ,  H03K3/356139

摘要： Integrated circuits with communications circuitry are provided. The communications circuitry may include at least first and second flip-flops connected in a chain along a data path. The first flip-flop may be controlled by a clock signal. The clock signal may be fed to a delay matching circuit. The delay matching circuit may provide a delayed version of the clock signal that controls the second flip-flop. The delay provided by the delay matching circuit may be equal to a clock-to-output delay of the first flip-flop. The delay matching circuit may have the same physical arrangement as the first flip-flop. The first and second flip-flops and the delay matching circuit may include dynamic sense amplifier flip-flops. The delay matching circuit may have an input that receives a high signal, a control input that receives the clock signal, and an output over which the delayed clock signal is provided.

摘要翻译： 提供具有通信电路的集成电路。 通信电路可以包括沿着数据路径连接在链中的至少第一和第二触发器。 第一触发器可以由时钟信号控制。 时钟信号可以馈送到延迟匹配电路。 延迟匹配电路可以提供控制第二触发器的时钟信号的延迟版本。 由延迟匹配电路提供的延迟可以等于第一触发器的时钟到输出延迟。 延迟匹配电路可以具有与第一触发器相同的物理布置。 第一和第二触发器和延迟匹配电路可以包括动态读出放大器触发器。 延迟匹配电路可以具有接收高信号的输入端，接收时钟信号的控制输入端和提供延迟时钟信号的输出端。

公开(公告)号：US08446172B2

公开(公告)日：2013-05-21

申请号：US13102918

申请日：2011-05-06

申请人： Allen Chan ,  Wilson Wong

发明人： Allen Chan ,  Wilson Wong

IPC分类号： H03K19/0175

CPC分类号： H04B3/06 ,  H04L25/0272 ,  H04L25/03343

摘要： One embodiment relates to a method of driving a transmission signal with pre-emphasis having minimal voltage jitter. A digital data signal is received, and a pre-emphasis signal is generated. The pre-emphasis signal may be a phase shifted and scaled version of the digital data signal. An output signal is generated by adding the pre-emphasis signal to the digital data signal within a driver switch circuit while low-pass filtering is applied to current sources of the driver switch circuit. Other embodiments, aspects, and features are also disclosed.

摘要翻译： 一个实施例涉及一种驱动具有最小电压抖动的预加重的传输信号的方法。 接收数字数据信号，产生预加重信号。 预加重信号可以是数字数据信号的相移和缩放版本。 通过在驱动器开关电路内的数字数据信号中加上预加重信号，同时对驱动器开关电路的电流源施加低通滤波来产生输出信号。 还公开了其它实施例，方面和特征。

公开(公告)号：US20130009279A1

公开(公告)日：2013-01-10

申请号：US13617347

申请日：2012-09-14

申请人： Weiqi Ding ,  Sergey Shumarayev ,  Wilson Wong ,  Ali Atesoglu ,  Sharat Babu Ippili

发明人： Weiqi Ding ,  Sergey Shumarayev ,  Wilson Wong ,  Ali Atesoglu ,  Sharat Babu Ippili

IPC分类号： H01L27/08 ,  H01L21/20

CPC分类号： H03B5/1212 ,  H01F2021/125 ,  H01F2027/2809 ,  H01L2924/0002 ,  H03B5/1243 ,  H03B5/1268 ,  H01L2924/00

摘要： Integrated circuits with phase-locked loops are provided. Phase-locked loops may include an oscillator, a phase-frequency detector, a charge pump, a loop filter, a voltage-controlled oscillator, and a programmable divider. The voltage-controlled oscillator may include multiple inductors, an oscillator circuit, and a buffer circuit. A selected one of the multiple inductors may be actively connected to the oscillator circuit. The voltage-controlled oscillators may have multiple oscillator circuits. Each oscillator circuit may be connected to a respective inductor, may include a varactor, and may be powered by a respective voltage regulator. Each oscillator circuit may be coupled to a respective input transistor pair in the buffer circuit through associated coupling capacitors. A selected one of the oscillator circuits may be turned on during normal operation by supplying a high voltage to the selected one of the oscillator circuit and by supply a ground voltage to the remaining oscillator circuits.

摘要翻译： 提供具有锁相环的集成电路。 锁相环可以包括振荡器，相位频率检测器，电荷泵，环路滤波器，压控振荡器和可编程分频器。 压控振荡器可以包括多个电感器，振荡器电路和缓冲电路。 多个电感器中选择的一个可以主动地连接到振荡器电路。 压控振荡器可以具有多个振荡器电路。 每个振荡器电路可以连接到相应的电感器，可以包括变容二极管，并且可以由相应的电压调节器供电。 每个振荡器电路可以通过相关联的耦合电容器耦合到缓冲电路中的相应输入晶体管对。 所选择的一个振荡器电路可以在正常操作期间通过向所选振荡器电路中的一个提供高电压并且向剩余的振荡器电路提供接地电压而导通。

公开(公告)号：US08335249B1

公开(公告)日：2012-12-18

申请号：US12626379

申请日：2009-11-25

申请人： Xiaoyan Su ,  Sriram Narayan ,  Wilson Wong ,  Sergey Shumarayev

发明人： Xiaoyan Su ,  Sriram Narayan ,  Wilson Wong ,  Sergey Shumarayev

IPC分类号： H03H7/40

CPC分类号： H04L25/03878 ,  H04L25/0272 ,  H04L25/061

摘要： Equalizer circuitry on an integrated circuit (“IC”) includes first, second, and third continuous time, equalizer stages connected in series. Each stage includes peaking inductor circuitry. The equalizer circuitry may further include controllably variable, static, DC mode offset voltage compensation circuitry and/or dynamic, continuous mode, offset voltage compensation circuitry for respectively reducing DC voltage offset and/or time-varying, continuous mode voltage offset between an output of the third equalizer stage and utilization circuitry to which that output is applied. The first equalizer stage may be preceded by termination circuitry having controllably variable impedance. Differential circuitry and signalling may be used for various circuit components. The equalizer circuitry is particularly useful for fabrication as part of a programmable IC, using 28 nm CMOS technology, and as a receiver equalizer for a high-speed serial data signal having a bit rate of 20-25 Gbps.

摘要翻译： 集成电路（IC）上的均衡器电路包括串联连接的第一，第二和第三连续时间的均衡器级。 每个阶段包括峰值电感电路。 均衡器电路可以进一步包括可控制的，静态的，直流模式偏移电压补偿电路和/或动态连续模式偏移电压补偿电路，用于分别减小DC电压偏移和/或时变，连续模式电压偏移 应用该输出的第三均衡器级和利用电路。 第一均衡器级可以在具有可控制可变阻抗的终端电路之前。 差分电路和信令可用于各种电路组件。 均衡器电路对于使用28nm CMOS技术的可编程IC的一部分进行制造以及作为具有20-25Gbps的比特率的高速串行数据信号的接收机均衡器是特别有用的。

公开(公告)号：US20120256670A1

公开(公告)日：2012-10-11

申请号：US13083431

申请日：2011-04-08

申请人： Weiqi Ding ,  Sergey Shumarayev ,  Wilson Wong ,  Tim Tri Hoang ,  Yanjing Ke

发明人： Weiqi Ding ,  Sergey Shumarayev ,  Wilson Wong ,  Tim Tri Hoang ,  Yanjing Ke

IPC分类号： H03K3/017

CPC分类号： H03K5/1565 ,  H03K3/017 ,  H03K5/12 ,  H03M9/00

摘要： A transmitter circuit is operable to provide an output signal in response to a first periodic signal. A multiplexer circuit is operable to provide a second periodic signal as a selected signal during a first phase of operation. The multiplexer circuit is operable to provide the output signal of the transmitter circuit as the selected signal during a second phase of operation. A sampler circuit is operable to generate first samples of the selected signal during the first phase of operation. The sampler circuit is operable to generate second samples of the selected signal during the second phase of operation. A duty cycle control circuit is operable to adjust a duty cycle of the first periodic signal based on the first and the second samples.

摘要翻译： 发射机电路可操作以响应于第一周期性信号提供输出信号。 多路复用器电路可操作以在第一操作阶段期间提供作为选定信号的第二周期信号。 多路复用器电路可操作以在第二操作阶段期间将发射机电路的输出信号提供为所选择的信号。 采样器电路可操作以在第一操作阶段产生所选信号的第一采样。 采样器电路可操作以在第二操作阶段期间产生所选信号的第二采样。 占空比控制电路可操作以基于第一和第二采样来调整第一周期信号的占空比。

公开(公告)号：US08155180B2

公开(公告)日：2012-04-10

申请号：US12358459

申请日：2009-01-23

申请人： Wilson Wong ,  Sergey Shumarayev ,  Rakesh Patel

发明人： Wilson Wong ,  Sergey Shumarayev ,  Rakesh Patel

IPC分类号： H03H7/30

CPC分类号： H04L1/205 ,  H04B17/21 ,  H04B17/24 ,  H04B17/309 ,  H04L25/03006

摘要： A system includes a programmable transmitter device (e.g., a PLD) connected to a programmable receiver device (e.g., another PLD) via a transmission medium for transmitting a high-speed data signal from the transmitter to the receiver. During a test mode of operation a low-speed communication link between the transmitter and receiver allows those devices to work together to transmit test signals having known characteristics from the transmitter to the receiver via the transmission medium, to analyze the test signals as received by the receiver, and to adjust at least some aspect of the system (e.g., equalizer circuitry in the receiver) to at least partly compensate for losses in the test signals as received by the receiver.

摘要翻译： 系统包括经由用于从发射机向接收机发送高速数据信号的传输介质连接到可编程接收机设备（例如，另一个PLD）的可编程发射机设备（例如，PLD）。 在测试操作模式期间，发射机和接收机之间的低速通信链路允许这些设备一起工作，以经由传输介质从发射机向接收机发送具有已知特性的测试信号，以分析由 接收器，并且至少部分地补偿由接收器接收的测试信号中的损耗，系统的至少一些方面（例如，接收机中的均衡器电路）。

公开(公告)号：US08126079B1

公开(公告)日：2012-02-28

申请号：US11824862

申请日：2007-07-03

申请人： Thungoc M. Tran ,  Sergey Shumarayev ,  Tim Tri Hoang ,  Weiqi Ding ,  Wilson Wong ,  Allen Chan

发明人： Thungoc M. Tran ,  Sergey Shumarayev ,  Tim Tri Hoang ,  Weiqi Ding ,  Wilson Wong ,  Allen Chan

IPC分类号： H04L27/00

CPC分类号： H04L7/033 ,  H03L7/22 ,  H04L7/0008

摘要： High-speed serial data signal transmitter and/or receiver circuitry is able to dynamically switch between handling data at two (or more) different data rates. Such a switch can be made very rapidly and with no requirement for reprogramming or reconfiguring the circuitry. Circuitry for glitchlessly switching between clock signals having different frequencies is also provided and may be used in the above-mentioned transmitter and/or receiver circuitry.

摘要翻译： 高速串行数据信号发射机和/或接收机电路能够以两种（或多种）不同的数据速率在处理数据之间动态切换。 这样的开关可以非常快速地进行，并且不需要重新编程或重新配置电路。 还提供了用于在具有不同频率的时钟信号之间无差错地切换的电路，并且可以在上述发射机和/或接收机电路中使用。

公开(公告)号：US08035453B1

公开(公告)日：2011-10-11

申请号：US12577568

申请日：2009-10-12

申请人： Wilson Wong ,  Allen Chan ,  Simardeep Maangat ,  Sergey Shumarayev

发明人： Wilson Wong ,  Allen Chan ,  Simardeep Maangat ,  Sergey Shumarayev

IPC分类号： H03K3/03 ,  H03L1/00 ,  H03L7/099

CPC分类号： H03K3/0322 ,  H03L7/0995 ,  H03L2207/06

摘要： An oscillator circuit includes differential variable delay circuits coupled together to form a ring oscillator. Each of the differential variable delay circuits has first and second inputs and first, second, third, and fourth transistors. A constant supply voltage is provided to sources of the first and the second transistors in each of the differential variable delay circuits. A variable supply voltage is provided to sources of the third and the fourth transistors in each of the differential variable delay circuits. Gates of the first and the third transistors are coupled to the first input. Gates of the second and the fourth transistors are coupled to the second input. The oscillator circuit generates a periodic output signal having a frequency that varies based on changes in the variable supply voltage.

摘要翻译： 振荡器电路包括耦合在一起以形成环形振荡器的差分可变延迟电路。 每个差分可变延迟电路具有第一和第二输入以及第一，第二，第三和第四晶体管。 在每个差分可变延迟电路中，向第一和第二晶体管的源极提供恒定的电源电压。 可变电源电压被提供给每个差分可变延迟电路中的第三和第四晶体管的源极。 第一和第三晶体管的栅极耦合到第一输入端。 第二和第四晶体管的栅极耦合到第二输入端。 振荡器电路产生具有基于可变电源电压的变化而变化的频率的周期性输出信号。

公开(公告)号：US07956696B2

公开(公告)日：2011-06-07

申请号：US12234114

申请日：2008-09-19

申请人： Tim Tri Hoang ,  Wilson Wong ,  Sergey Shumarayev

发明人： Tim Tri Hoang ,  Wilson Wong ,  Sergey Shumarayev

IPC分类号： H03L7/085 ,  H03B19/00

CPC分类号： H03L7/099 ,  H03L7/18

摘要： A circuit includes phase detection circuitry, a clock signal generation circuit, a first frequency divider, and a second frequency divider. The phase detection circuitry compares an input clock signal to a feedback signal to generate a control signal. The clock signal generation circuit generates a periodic output signal in response to the control signal. The first frequency divider divides a frequency of the periodic output signal by a first value to generate a first frequency divided signal. The second frequency divider divides the frequency of the periodic output signal by a second value to generate a second frequency divided signal. The first and the second frequency divided signals are routed to the phase detection circuitry as the feedback signal during different time intervals.

摘要翻译： 电路包括相位检测电路，时钟信号发生电路，第一分频器和第二分频器。 相位检测电路将输入时钟信号与反馈信号进行比较以产生控制信号。 时钟信号产生电路响应于控制信号产生周期性输出信号。 第一分频器将周期性输出信号的频率除以第一值，以产生第一分频信号。 第二分频器将周期性输出信号的频率除以第二值，以产生第二分频信号。 在不同的时间间隔期间，第一和第二分频信号作为反馈信号被路由到相位检测电路。

公开(公告)号：US07944235B1

公开(公告)日：2011-05-17

申请号：US12709360

申请日：2010-02-19

申请人： Sergey Shumarayev ,  Thungoc M. Tran ,  Simardeep Maangat ,  Wilson Wong

发明人： Sergey Shumarayev ,  Thungoc M. Tran ,  Simardeep Maangat ,  Wilson Wong

IPC分类号： H03K19/173

CPC分类号： H03K19/17744

摘要： High-speed serial interface (“HSSI”) transceiver circuitry (e.g., on a programmable logic device (“PLD”) integrated circuit) includes input buffer circuitry with adaptive equalization capability. The transceiver circuitry also includes an output driver, which may include pre-emphasis capability (preferably controllably settable). Selectively usable loop-back circuitry is provided for allowing the output signal of the input buffer to be applied substantially directly to the output driver. The loop-back circuitry may include a loop-back driver, which may be turned on substantially only when needed for loop-back operations.

摘要翻译： 高速串行接口（“HSSI”）收发器电路（例如，在可编程逻辑器件（“PLD”）集成电路上）包括具有自适应均衡能力的输入缓冲器电路。 收发器电路还包括输出驱动器，其可以包括预加重功能（优选可控地设置）。 提供了可选择的环回电路，用于使输入缓冲器的输出信号基本上直接施加到输出驱动器。 环回电路可以包括环回驱动器，其可以基本上仅在环回操作需要时被导通。