公开(公告)号：US11810977B2

公开(公告)日：2023-11-07

申请号：US17219195

申请日：2021-03-31

申请人： NANYA TECHNOLOGY CORPORATION

发明人： Teng-Yen Huang

IPC分类号： H01L29/78 ,  H01L21/768 ,  H01L29/66

CPC分类号： H01L29/785 ,  H01L21/76816 ,  H01L21/76877 ,  H01L29/66795 ,  H01L29/7848

摘要： The present disclosure provides a semiconductor device. The semiconductor device includes a semiconductor substrate, a semiconductor fin and a filled trench. The semiconductor fin extends upwards from the semiconductor substrate. The filled trench is formed in the semiconductor fin and includes a first sigma portion, a second sigma portion and a middle portion. The first sigma portion is partially filled by a semiconductor buffer region, and an unfilled part of the first sigma portion is filled by a doped semiconductor region grown on the semiconductor buffer region. The second sigma portion is filled by the semiconductor buffer region. The middle portion connects the first sigma portion to the second sigma portion, and the middle portion is filled by the semiconductor buffer region.

公开(公告)号：US11802910B1

公开(公告)日：2023-10-31

申请号：US17742629

申请日：2022-05-12

申请人： NANYA TECHNOLOGY CORPORATION

发明人： Wu-Der Yang

IPC分类号： G01R31/28 ,  G01R1/04

CPC分类号： G01R31/2889 ,  G01R1/0458 ,  G01R31/2887

摘要： A probe apparatus for testing a semiconductor device is provided. The testing device includes a socket having a cavity for accommodating a device under test (DUT), and a cover disposed on the socket. The socket includes a thermal conductive material. The cover includes a plate, a circuit board attached to the plate, and an opening penetrating the plate and the circuit board, exposing the cavity of the socket.

公开(公告)号：US20230343841A1

公开(公告)日：2023-10-26

申请号：US18217719

申请日：2023-07-03

申请人： NANYA TECHNOLOGY CORPORATION

发明人： TSE-YAO HUANG

IPC分类号： H01L29/417 ,  H01L29/40 ,  H01L29/45 ,  H01L29/80 ,  H01L23/532 ,  H01L29/78

CPC分类号： H01L29/41775 ,  H01L29/401 ,  H01L29/45 ,  H01L29/458 ,  H01L29/806 ,  H01L29/41725 ,  H01L23/53271 ,  H01L29/456 ,  H01L29/7839

摘要： The present disclosure relates to a semiconductor device with a contact structure and a method for preparing the semiconductor device. The semiconductor device includes a source/drain structure disposed over a semiconductor substrate, and a dielectric layer disposed over the source/drain structure. The semiconductor device also includes a polysilicon stack disposed over the source/drain structure and surrounded by the dielectric layer. The polysilicon stack includes a first polysilicon layer and a second polysilicon layer disposed over the first polysilicon layer. The first polysilicon layer is undoped, and the second polysilicon layer is doped. The semiconductor device further includes a contact structure disposed directly over the polysilicon stack and surrounded by the dielectric layer.

公开(公告)号：US11798602B1

公开(公告)日：2023-10-24

申请号：US17741884

申请日：2022-05-11

申请人： NANYA TECHNOLOGY CORPORATION

发明人： Wu-Der Yang

IPC分类号： G11C7/10

CPC分类号： G11C7/1087 ,  G11C7/109 ,  G11C2207/12

摘要： A data receiving circuit is provided. The data receiving circuit includes a data input circuit, a latch circuit, and an equalizer. The data input circuit is configured to receive an input signal, and the latch circuit is connected to the data input circuit and configured to output an output signal in response to the input signal. The equalizer includes a first transistor having a source connected to latch circuit; and

a second transistor having a source connected to the latch circuit and a gate connected to a gate of the first transistor.

公开(公告)号：US11791399B2

公开(公告)日：2023-10-17

申请号：US17516690

申请日：2021-11-01

申请人： NANYA TECHNOLOGY CORPORATION

发明人： Tse-Yao Huang

IPC分类号： H01L29/66 ,  H01L29/49 ,  H01L29/51

CPC分类号： H01L29/6656 ,  H01L29/4916 ,  H01L29/515

摘要： The present application discloses a method for fabricating semiconductor device with a graphene-based element. The method includes providing a substrate; forming a stacked gate structure over the substrate; forming first spacers on sidewalls of the gate stack structure, wherein the first spacers comprise graphene; forming sacrificial spacers on sidewall of the first spacers; and forming second spacers on sidewall of the sacrificial spacers.

公开(公告)号：US11789816B1

公开(公告)日：2023-10-17

申请号：US17737726

申请日：2022-05-05

申请人： NANYA TECHNOLOGY CORPORATION

发明人： Chun-Lu Lee

IPC分类号： G06F11/10 ,  G06F11/07 ,  H03K19/20 ,  G06F3/06

CPC分类号： G06F11/1068 ,  G06F3/0619 ,  G06F3/0659 ,  G06F3/0679 ,  G06F11/0772 ,  H03K19/20

摘要： The present disclosure provides a method for controlling a data storage device. The method includes: storing a first data in a first area of a memory of the data storage device; storing a second data in a second area of the memory, wherein the second data is associated with the first; reading the first data and the second data via a first communication interface; and in response to the read first data and second data, generating a first output signal.

公开(公告)号：US20230328970A1

公开(公告)日：2023-10-12

申请号：US17717367

申请日：2022-04-11

申请人： NANYA TECHNOLOGY CORPORATION

发明人： CHUN-CHI LAI

IPC分类号： H01L27/108 ,  H01L29/40 ,  H01L23/532 ,  H01L23/528 ,  H01L29/49 ,  H01L29/51 ,  H01L21/768

CPC分类号： H01L27/10891 ,  H01L29/401 ,  H01L23/53257 ,  H01L23/53295 ,  H01L23/528 ,  H01L23/53271 ,  H01L29/4916 ,  H01L29/495 ,  H01L29/517 ,  H01L21/76816 ,  H01L21/76829 ,  H01L21/76877

摘要： The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The method includes providing a substrate including an array area and a peripheral area adjacent to the array area, forming word line structures and source/drain regions in the array area, and a word line protection layer on the array area, forming a first hard mask layer over the substrate and having a step height adjacent to a border between the array area and the peripheral area, forming a bit line contact in the array area and between the word line structures by using the first hard mask layer as a pattern guide, and forming a gate electrode layer on the peripheral area. In some embodiments, the step of forming a word line structures in the array area includes forming a composite word line dielectric including a gate dielectric layer and a barrier liner; forming a lower electrode layer disposed over the composite word line dielectric; forming a graphene layer disposed over the lower electrode layer; and forming an upper electrode layer over the first graphene layer

公开(公告)号：US20230326957A1

公开(公告)日：2023-10-12

申请号：US17658448

申请日：2022-04-08

申请人： NANYA TECHNOLOGY CORPORATION

发明人： Shih-Ting HUANG

IPC分类号： H01L49/02 ,  H01L27/108

CPC分类号： H01L28/75 ,  H01L27/10808 ,  H01L27/10852 ,  H01L28/92 ,  H01L28/91

摘要： A method of forming a semiconductor structure includes following steps. A substrate is provided. The substrate has an active region, an isolation structure adjacent to the active region, and a contact on the active region. A dielectric stack is formed on the substrate. A poly layer is formed on the dielectric stack. The poly layer and the dielectric stack are etched to form an opening to expose the contact of the substrate. A conductive film is formed in the opening and an ALD oxide layer is deposited on a sidewall of the opening. In addition, a semiconductor structure is also disclosed herein.

公开(公告)号：US20230326956A1

公开(公告)日：2023-10-12

申请号：US18333507

申请日：2023-06-12

申请人： NANYA TECHNOLOGY CORPORATION

发明人： Ting-Cih KANG ,  Hsih-Yang CHIU

IPC分类号： H01L21/02 ,  H01G4/30 ,  H01L23/522

CPC分类号： H01L28/60 ,  H01L23/5223 ,  H01G4/30

摘要： A semiconductor structure includes a trench capacitor, a stacked capacitor, a first electrode plate, and a second electrode plate. The trench capacitor is located in a substrate, in which the trench capacitor has a first conductive structure and a first dielectric structure in contact with the first conductive structure. The stacked capacitor has a second conductive structure and a second dielectric structure in contact with the second conductive structure, in which the stacked capacitor is at least partially aligned with the trench capacitor in an axis vertical to a top surface of the substrate, and the first and second conductive structures are electrically connected. The trench capacitor and the stacked capacitor are electrically connected in parallel between the first and second electrode plates.

公开(公告)号：US20230326869A1

公开(公告)日：2023-10-12

申请号：US17716374

申请日：2022-04-08

申请人： NANYA TECHNOLOGY CORPORATION

发明人： CHUN-YEN WEI

IPC分类号： H01L23/544 ,  G03F1/42

CPC分类号： H01L23/544 ,  G03F1/42 ,  H01L2223/54426

摘要： A method for manufacturing a semiconductor device structure with overlay marks is provided. The method includes providing a substrate; forming a first light-emitting feature on the substrate; forming a first pattern on the first light-emitting feature; and forming a second pattern on the first pattern. The first light-emitting feature is configured to emit a light of a first wavelength, and the first pattern has a first transmittance to the light of the first wavelength, the second pattern has a second transmittance to the light of the first wavelength, and the first transmittance is different from the second transmittance.