Abstract:
The present invention is ripple cancellation circuitry used with a switching power supply, which provides direct current (DC) power via a DC power amplifier (PA) signal to an RF PA final stage. The DC PA signal includes a DC component and a power supply ripple component, which is generated as a result of the switching characteristics of the switching power supply and creates an output ripple in an RF output signal from the PA final stage. The ripple cancellation circuitry substantially cancels the output ripple by adding a ripple cancellation signal having a ripple component that is phase-shifted approximately 180 degrees from the output ripple to the RF output signal. The ripple cancellation circuitry uses a switching signal that is provided by the switching power supply to generate the ripple cancellation signal.
Abstract translation:本发明是与开关电源一起使用的纹波消除电路,其通过DC功率放大器(PA)信号向RF PA最终级提供直流(DC)功率。 DC PA信号包括作为开关电源的开关特性的结果产生的DC分量和电源纹波分量,并且在来自PA最终级的RF输出信号中产生输出纹波。 纹波消除电路基本上通过将具有从输出纹波相移大约180度的纹波分量的纹波消除信号加到RF输出信号来抵消输出纹波。 纹波消除电路使用由开关电源提供的开关信号来产生纹波消除信号。
Abstract:
The present invention is a wide dynamic range antenna switch that, when disabled, has a stable input impedance over a wide power range. The wide dynamic range antenna switch includes multiple transistors, which are coupled in series, to provide a main signal path between an antenna connection and a radio connection. Direct current (DC) bias signals are provided to each of the transistors to ensure than when the antenna switch is disabled, the input impedance is stable. A control input, which may operate with low voltage control signals, enables or disables the antenna switch. The antenna switch may be coupled with other antenna switches in a communications system with multiple transceivers sharing a common antenna, and with a wide range of transmitter output power levels. Different embodiments of the present invention provide different DC bias circuit architectures.
Abstract:
A system and method are provided for switching from one phase-locked loop feedback source to another in a radio frequency (RF) transmitter. The RF transmitter includes a phase-locked loop (PLL) that provides a phase-modulated RF input signal and power amplifier circuitry that amplifies the RF input signal to provide an RF output signal. The PLL includes switching circuitry that couples a feedback path of the PLL to an output of the PLL for open loop operation and couples the feedback path of the PLL to an output of the power amplifier circuitry for closed loop operation. Prior to switching the feedback path from the output of the PLL to the output of the power amplifier circuitry, time alignment circuitry operates to time-align feedback signals from the outputs of the PLL and the power amplifier circuitry such that switching from open loop operation to closed loop operation causes minimal phase disturbance.
Abstract:
The present invention is a parallel RF amplifier circuit that selects between a high power side (HPS) and a low power side (LPS), depending upon output power. A chain matching network couples an LPS output to an HPS output for improved efficiency at lower output power. When the HPS is selected, the LPS output is disabled, and when the LPS is selected, the HPS output is disabled When the HPS is selected, large signal voltage swings from the collector of the HPS amplifier may be multiplied through the chain matching network, and may cause negative voltage swings at the LPS collector, which may degrade linearity and efficiency of the HPS amplifier by driving currents into the disabled LPS amplifier. Therefore, the present invention includes LPS bias circuitry to minimize impacts of negative voltage swings at the LPS output.
Abstract:
An efficient power amplifier circuitry for a mobile terminal or similar wireless communication device is provided. The power amplifier circuitry includes an output stage configured as a collector controlled Doherty amplifier, wherein the collector controlled Doherty amplifier increases the efficiency of the power amplifier at backoff power levels. The output stage includes main and peaking amplifiers connected in parallel and operating 90 degrees out-of-phase. The main amplifier is controlled using a first variable supply voltage, and the peaking amplifier is controlled using a second variable supply voltage. The first and second variable supply voltages are provided such that the main amplifier is active and the peaking amplifier is inactive for output power levels less than a predetermined backoff from a maximum output power level, and both the main amplifier and peaking amplifiers are active and operating in concert for output power levels greater than the predetermined backoff.
Abstract:
A system and method are provided for efficiently amplifying a radio frequency signal. In general, the system includes power amplifier circuitry that efficiently amplifies an input signal under power back-off conditions. In one embodiment, the power amplifier circuitry has an efficiency of at least 30% at a 6 dB back-off point. In addition, DC-DC conversion circuitry operates to control a variable supply voltage provided to the power amplifier circuitry, thereby controlling an output power level, or average output power, of the power amplifier circuitry.
Abstract:
A system and method for performing DC offset correction in a wireless communication receiver during “dead time” are provided. The receiver includes amplifier circuitry that amplifies a received radio frequency (RF) signal, downconversion circuitry that downconverts the received RF signal to provide a downconverted signal, digitization circuitry that digitizes the downconverted signal to provide a digital signal, and digital DC offset correction circuitry enabled during the dead time when there should be no DC content in the downconverted signal. In operation, the digital DC offset correction circuitry detects a DC offset of the digital signal and subtracts the DC offset from the digital signal.
Abstract:
A mobile terminal including a multi-phase DC-DC converter for controlling a supply voltage provided to a power amplifier in the transmit chain. In general, the multi-phase DC-DC converter includes a multi-phase converter control system and a multi-phase power train. The multi-phase converter control system generates a plurality of control signals based on a set-point voltage and a supply voltage at the output of the multi-phase DC-DC converter. The plurality of control signals are provided to the multi-phase control system which generates a plurality of currents each based on a corresponding one of the plurality of control signals. The plurality of currents charge an output capacitor such that an average voltage across the output capacitor is the desired supply voltage.
Abstract:
The present invention is a differential transconductance amplifier circuit that includes matched cross-coupled transconductance elements connected such that the differential gain of the amplifier is determined by only passive elements. By virtually eliminating the effects of active elements on the amplifier gain, the amplifier operates in a very linear manner over its entire operating range. Power consumption, amplifier noise level, and dynamic range can be optimized with appropriate selection of the passive elements that determine amplifier gain.
Abstract:
A system providing a phase or frequency modulated signal is provided. In general, the system includes a phase locked loop (PLL) having a fractional-N divider in a reference path of the PLL operating to divide a reference frequency based on a pre-distorted modulation signal. Pre-distortion circuitry operates to provide the pre-distorted modulation signal by pre-distorting a modulation signal such that a convolution, or cascade, of the pre-distortion and a transfer function of the PLL results in a substantially flat frequency response for a range of modulation rates greater than a bandwidth of the PLL.