公开(公告)号：US20090072910A1

公开(公告)日：2009-03-19

申请号：US12112914

申请日：2008-04-30

Applicant: Lalitkumar Nathawad ,  Justin Hwang

Inventor： Lalitkumar Nathawad ,  Justin Hwang

IPC: H03B5/18 ,  H03L7/06

CPC classification number: H03L7/099 ,  H03B5/1212 ,  H03B5/1228 ,  H03B5/1253 ,  H03B5/1265 ,  H03B2201/025 ,  H03J2200/10

Abstract: A voltage-controlled oscillator (VCO) comprising a first circuit, a second circuit, a comparator circuit, and a control unit. The first circuit can determine an output common mode voltage associated with an output of the VCO. The second circuit can generate an upper control voltage limit and a lower control voltage limit associated with a control voltage received by the VCO based, at least in part, on the output common mode voltage. The comparator circuit can compare the control voltage to the upper and lower control voltage limits. The control unit can determine whether to change a switched capacitance associated with the VCO based, at least in part, on whether the control voltage is outside the upper and lower control voltage limits, thereby maintaining an optimal region of operation for the control voltage.

Abstract translation: 一种包括第一电路，第二电路，比较器电路和控制单元的压控振荡器（VCO）。 第一电路可以确定与VCO的输出相关联的输出共模电压。 第二电路可以至少部分地基于输出共模电压产生与VCO接收的控制电压相关联的较高控制电压限制和较低控制电压限制。 比较器电路可以将控制电压与上下限电压限制进行比较。 至少部分地基于控制电压是否超出上限和下限控制电压限制，控制单元可以确定是否改变与VCO相关联的开关电容，从而保持控制电压的最佳操作区域。

公开(公告)号：US20080174361A1

公开(公告)日：2008-07-24

申请号：US12054755

申请日：2008-03-25

Applicant: Ramon A. Gomez

Inventor： Ramon A. Gomez

IPC: G05F1/10

CPC classification number: H03L7/00 ,  H03B5/1212 ,  H03B5/1215 ,  H03B5/1228 ,  H03B5/1243 ,  H03B5/1253 ,  H03B5/1265 ,  H03B5/1278 ,  H03B2200/0046 ,  H03B2200/0048 ,  H03B2200/005 ,  H03B2201/02 ,  H03B2201/0208 ,  H03B2201/025 ,  H03D7/165 ,  H03D7/18 ,  H03J5/244 ,  H03J2200/10 ,  H03L7/0898 ,  H03L7/093 ,  H03L7/099 ,  H03L7/10 ,  H03L7/107 ,  H03L7/1072 ,  H03L7/18

Abstract: A gain compensator compensates for the gain variation of a varactor-tuned voltage tuned oscillator (VCO) in a phase lock loop (PLL). The VCO includes a parallel LC circuit having multiple fixed capacitors that can be switched-in or switched-out of the LC circuit according to a capacitor control signal to perform band-select tuning of the VCO. The gain compensator compensates for the variable VCO gain by generating a charge pump reference current that is based on the same capacitor control signal that controls the fixed capacitors in the LC circuit. The gain compensator generates the charge pump reference current by replicating a reference scale current using unit current sources. The number of times the reference scale current is replicated is based on the fixed capacitance that is switched-in to the LC circuit and therefore the frequency band of the PLL. The reference scale current is generated based on a PLL control that specifics certain PLL characteristics such as reference frequency, loop bandwidth, and loop damping. Therefore, the reference pump current can be efficiently optimized for changing PLL operating conditions, in addition to compensating for variable VCO gain.

Abstract translation: 增益补偿器补偿锁相环（PLL）中变容二极管调谐电压调谐振荡器（VCO）的增益变化。 VCO包括具有多个固定电容器的并联LC电路，其可以根据电容器控制信号切换或切换出LC电路，以执行VCO的频带选择调谐。 增益补偿器通过产生基于控制LC电路中的固定电容器的相同电容器控制信号的电荷泵参考电流来补偿可变VCO增益。 增益补偿器通过使用单位电流源复制参考刻度电流来产生电荷泵参考电流。 参考比例电流复制的次数是基于切换到LC电路的固定电容，因此是PLL的频带。 参考比例电流是基于特定于参考频率，环路带宽和环路阻尼等特定PLL特性的PLL控制产生的。 因此，除了补偿可变VCO增益之外，参考泵电流可以有效地优化用于改变PLL工作条件。

公开(公告)号：US07330079B2

公开(公告)日：2008-02-12

申请号：US11263304

申请日：2005-10-31

Applicant: Louis Albert Williams, III ,  Francesco Cavaliere

Inventor： Louis Albert Williams, III ,  Francesco Cavaliere

IPC: H03L7/08

CPC classification number: H03L7/085 ,  H03B2201/025 ,  H03J2200/10 ,  H03L7/099 ,  H03L7/1976

Abstract: A controller for an adjustable-frequency oscillator includes a first counter supplied with a stop-count value to count adjustable-frequency oscillator cycles divided by the ratio of desired frequency to reference oscillator frequency, to produce a stop signal when the first counter reaches the stop-count value. A second counter counts cycles of a reference oscillator starting from an initial number related to the stop-count value. The second counter stops counting and produces an end-count when the second counter receives the stop signal from the first counter. A resonant tank circuit includes a bank of capacitors with switches to select resonant tank circuit capacitors. The switches are selectively controlled using the end-count in the second counter. The stop-count value is set for the first counter so that the end count number in the second counter using a ones-complement binary format can be used to iteratively set the switches with minimal digital computation.

Abstract translation: 用于可调频率振荡器的控制器包括：第一计数器，其提供停止计数值，以将可调频率振荡器周期除以所需频率与参考振荡器频率的比率，以在第一计数器到达停止时产生停止信号 - 数值。 第二个计数器从与停止计数值相关的初始数字开始计数参考振荡器的周期。 当第二计数器从第一计数器接收到停止信号时，第二计数器停止计数并产生结束计数。 谐振回路包括一组电容器，开关用于选择谐振回路电容器。 使用第二计数器中的结束计数来选择性地控制开关。 为第一计数器设置停止计数值，使得使用单补码二进制格式的第二计数器中的结束计数值可以用于以最小的数字计算来迭代地设置开关。

公开(公告)号：US07301407B2

公开(公告)日：2007-11-27

申请号：US11061801

申请日：2005-02-18

Applicant: Je-Kwang Cho

Inventor： Je-Kwang Cho

IPC: H03L7/00

CPC classification number: H03B5/1215 ,  H03B5/1228 ,  H03B2201/025 ,  H03J2200/10

Abstract: A capacitor bank includes a first node, a second node, first blocking capacitors, N first AMOS varactors, second blocking capacitors and N second AMOS varactors. The first blocking capacitors have first terminals connected to the first node and second terminals where a bias voltage is applied. The N first AMOS varactors have first terminals connected to the second terminals of the first block capacitors. The second blocking capacitors have first terminals connected to the second node and second terminals where the bias voltage is applied. The N second AMOS varactors have first terminals connected to the second terminals of the second blocking capacitors and second terminals connected to second terminals of the first AMOS varactors, respectively, wherein N binary coded signals are applied to the respective second terminals of the first AMOS varactors and the second AMOS varactors. Therefore, phase-noise degradation caused by the FM modulation may be avoided.

Abstract translation: 电容器组包括第一节点，第二节点，第一阻塞电容器，N个第一AMOS变容二极管，第二阻塞电容器和N个第二AMOS变容二极管。 第一隔离电容器具有连接到第一节点的第一端子和施加偏置电压的第二端子。 N个第一AMOS变容二极管具有连接到第一块电容器的第二端子的第一端子。 第二隔离电容器具有连接到第二节点的第一端子和施加偏置电压的第二端子。 N个第二AMOS变容二极管分别具有连接到第二隔离电容器的第二端子的第一端子和分别连接到第一AMOS变容二极管的第二端子的第二端子，其中N个二进制编码信号被施加到第一AMOS变容二极管的相应的第二端子 和第二个AMOS变容二极管。 因此，可以避免由FM调制引起的相位噪声劣化。

公开(公告)号：US07276970B2

公开(公告)日：2007-10-02

申请号：US11131281

申请日：2005-05-18

Applicant: Haideh Khorramabadi

Inventor： Haideh Khorramabadi

IPC: H03F3/45

CPC classification number: H03L7/23 ,  H01F17/0006 ,  H01F17/0013 ,  H01F2017/0053 ,  H01F2021/125 ,  H01L23/5227 ,  H01L27/0248 ,  H01L27/08 ,  H01L2924/0002 ,  H01L2924/3011 ,  H03B5/1215 ,  H03B5/1228 ,  H03B5/364 ,  H03B2201/025 ,  H03B2201/0266 ,  H03D7/161 ,  H03D7/18 ,  H03F1/3211 ,  H03F1/52 ,  H03F3/191 ,  H03F3/45183 ,  H03F3/45188 ,  H03F3/45475 ,  H03F2200/294 ,  H03F2203/45318 ,  H03F2203/45704 ,  H03G1/0029 ,  H03H11/1291 ,  H03J1/0075 ,  H03J3/04 ,  H03J3/08 ,  H03J3/185 ,  H03J2200/10 ,  H03L1/023 ,  H03L7/10 ,  H03L7/18 ,  H01L2924/00

Abstract: An integrated receiver with channel selection and image rejection substantially implemented on a single CMOS integrated circuit. A receiver front end provides programable attenuation and a programable gain low noise amplifier. LC filters integrated onto the substrate in conjunction with image reject mixers provide image frequency rejection. Filter tuning and inductor Q compensation over temperature are performed on chip. Active filters utilize multi track spiral inductors with shields to increase circuit Q. The filters incorporate a gain stage that provides improved dynamic range through the use of cross coupled auxiliary differential pair CMOS amplifiers to cancel distortion in a main linearized differential pair amplifier. Frequency planning provides additional image rejection. Local oscillator signal generation methods on chip reduce distortion. A PLL generates needed out of band LO signals. Direct synthesis generates in band LO signals. PLL VCOs are centered automatically. A differential crystal oscillator provides a frequency reference. Differential signal transmission throughout the receiver is used. ESD protection is provided by a pad ring and ESD clamping structure. Shunts utilize a gate boosting at each pin to discharge ESD build up. An IF VGA utilizes distortion cancellation achieved with cross coupled differential pair amplifiers having their Vds dynamically modified in conjunction with current steering of the differential pairs sources.

Abstract translation: 具有通道选择和图像抑制的集成接收器基本上在单个CMOS集成电路上实现。 接收机前端提供可编程衰减和可编程增益低噪声放大器。 与图像抑制混合器一起集成到衬底上的LC滤波器提供图像频率抑制。 过滤器调谐和电感Q补偿温度在芯片上执行。 有源滤波器利用具有屏蔽的多轨螺旋电感器来增加电路Q.滤波器包括增益级，其通过使用交叉耦合辅助差分对CMOS放大器来消除主线性化差分对放大器中的失真而提供改进的动态范围。 频率规划提供额外的镜像抑制。 本地振荡器信号产生方法在芯片上减少失真。 PLL产生所需的带外LO信号。 直接合成产生带内LO信号。 PLL VCO自动居中。 差分晶体振荡器提供频率参考。 使用整个接收机的差分信号传输。 ESD保护由衬垫环和ESD夹紧结构提供。 分流器利用每个引脚上的门极升压来放电ESD积聚。 IF VGA利用交叉耦合的差分对放大器实现的失真消除，其具有与差分对源的当前转向结合动态修改的V ds。

公开(公告)号：US20070222528A1

公开(公告)日：2007-09-27

申请号：US11805368

申请日：2007-05-23

Applicant: Scott Pernia ,  Michael McCorquodale ,  Sundus Kubba ,  Justin O'Day ,  Gordon Carichner ,  Eric Marsman

Inventor： Scott Pernia ,  Michael McCorquodale ,  Sundus Kubba ,  Justin O'Day ,  Gordon Carichner ,  Eric Marsman

IPC: G01R23/00

CPC classification number: H03L1/022 ,  H03B5/1212 ,  H03B5/1221 ,  H03B5/1228 ,  H03B5/124 ,  H03B2200/0038 ,  H03B2201/025 ,  H03J2200/10 ,  H03L1/023 ,  H03L7/089

Abstract: Exemplary embodiments of the invention provide a reference harmonic oscillator integrated circuit having three or more terminals, with systems and methods for calibrating the harmonic oscillator to a selected first frequency using a limited number of terminals. An exemplary apparatus comprises: a reference harmonic oscillator, a first terminal to receive a supply voltage, a second terminal to receive a ground potential, a third terminal to provide an output signal having an output frequency, and may also include a fourth terminal. One of the first, second, third or fourth terminals is further adapted for input of a calibration of the first frequency. The exemplary apparatus may enter calibration and testing modes in response to various commands such as a calibration mode signal, and may also be configured through one of the terminals for output frequency selection, spread-spectrum output, and output voltage levels.

Abstract translation: 本发明的示例性实施例提供了具有三个或更多个端子的参考谐波振荡器集成电路，其具有使用有限数量的端子将谐波振荡器校准为所选择的第一频率的系统和方法。 示例性装置包括：参考谐波振荡器，用于接收电源电压的第一端子，用于接收地电位的第二端子，第三端子以提供具有输出频率的输出信号，并且还可以包括第四端子。 第一，第二，第三或第四端子中的一个进一步适于输入第一频率的校准。 示例性装置可以响应于诸如校准模式信号的各种命令而进入校准和测试模式，并且还可以通过用于输出频率选择，扩频输出和输出电压电平的一个端子进行配置。

公开(公告)号：US07271622B2

公开(公告)日：2007-09-18

申请号：US11473620

申请日：2006-06-22

Applicant: Emmanuel Metaxakis

Inventor： Emmanuel Metaxakis

IPC: H03B5/12 ,  G01R25/00

CPC classification number: H03L7/00 ,  H03B5/1215 ,  H03B5/1231 ,  H03B5/124 ,  H03B27/00 ,  H03B2201/025 ,  H03J2200/10

Abstract: In wireless application there is made use of a quadrature oscillators that generate signals that are capable of oscillating at quadrature of each other. The quadrature oscillator is comprised of two differential modified Colpitts oscillators. A capacitor bank allows for the selection of a desired frequency from a plurality of discrete possible frequencies. The quadrature oscillator is further coupled with a phase-error detector connected at the point-of-use of the generated ‘I’ and ‘Q’ channels and through the control of current sources provides corrections means to ensure that the phase shift at the point-of-use remains at the desired ninety degrees.

Abstract translation: 在无线应用中，使用产生能够彼此正交振荡的信号的正交振荡器。 正交振荡器由两个差分改进的Colpitts振荡器组成。 电容器组允许从多个离散的可能频率中选择期望的频率。 正交振荡器还与在所产生的“I”和“Q”通道的使用点处连接的相位误差检测器耦合，并且通过电流源的控制提供校正装置以确保在点处的相移 - 使用保持在所需的九十度。

公开(公告)号：US07224234B2

公开(公告)日：2007-05-29

申请号：US11314618

申请日：2005-12-21

Applicant: Ramon A. Gomez

Inventor： Ramon A. Gomez

IPC: H03L7/00

CPC classification number: H03L7/00 ,  H03B5/1212 ,  H03B5/1215 ,  H03B5/1228 ,  H03B5/1243 ,  H03B5/1253 ,  H03B5/1265 ,  H03B5/1278 ,  H03B2200/0046 ,  H03B2200/0048 ,  H03B2200/005 ,  H03B2201/02 ,  H03B2201/0208 ,  H03B2201/025 ,  H03D7/165 ,  H03D7/18 ,  H03J5/244 ,  H03J2200/10 ,  H03L7/0898 ,  H03L7/093 ,  H03L7/099 ,  H03L7/10 ,  H03L7/107 ,  H03L7/1072 ,  H03L7/18

Abstract: A gain compensator compensates for the gain variation of a varactor-tuned voltage tuned oscillator (VCO) in a phase lock loop (PLL). The VCO includes a parallel LC circuit having multiple fixed capacitors that can be switched-in or switched-out of the LC circuit according to a capacitor control signal to perform band-select tuning of the VCO. The gain compensator compensates for the variable VCO gain by generating a charge pump reference current that is based on the same capacitor control signal that controls the fixed capacitors in the LC circuit. The gain compensator generates the charge pump reference current by replicating a reference scale current using unit current sources. The number of times the reference scale current is replicated is based on the fixed capacitance that is switched-in to the LC circuit and therefore the frequency band of the PLL. The reference scale current is generated based on a PLL control that specifics certain PLL characteristics such as reference frequency, loop bandwidth, and loop damping. Therefore, the reference pump current can be efficiently optimized for-changing PLL operating conditions, in addition to compensating for variable VCO gain.

Abstract translation: 增益补偿器补偿锁相环（PLL）中变容二极管调谐电压调谐振荡器（VCO）的增益变化。 VCO包括具有多个固定电容器的并联LC电路，其可以根据电容器控制信号切换或切换出LC电路，以执行VCO的频带选择调谐。 增益补偿器通过产生基于控制LC电路中的固定电容器的相同电容器控制信号的电荷泵参考电流来补偿可变VCO增益。 增益补偿器通过使用单位电流源复制参考刻度电流来产生电荷泵参考电流。 参考比例电流复制的次数是基于切换到LC电路的固定电容，因此是PLL的频带。 参考比例电流是基于特定于参考频率，环路带宽和环路阻尼等特定PLL特性的PLL控制产生的。 因此，除了补偿可变VCO增益之外，参考泵电流可以有效地优化用于改变PLL工作条件。

公开(公告)号：US20070001823A1

公开(公告)日：2007-01-04

申请号：US11259910

申请日：2005-10-27

Applicant: Lawrence Der ,  Dana Taipale ,  Scott Willingham

Inventor： Lawrence Der ,  Dana Taipale ,  Scott Willingham

IPC: G08B3/00

CPC classification number: H03B5/32 ,  H03B2201/025 ,  H03D7/165 ,  H03J1/0008 ,  H03J2200/10

Abstract: In one embodiment, the present invention includes a method for determining if a frequency control instruction would cause a first capacitor bank to reach a limit and adjusting the first capacitor bank in a first direction using a calibration value and adjusting a second capacitor bank in a second direction if the first capacitor bank would reach the limit. Furthermore, the calibration value may be calculated and stored in accordance with other embodiments. In such manner, small changes in capacitance and correspondingly small changes in frequency may be effected.

Abstract translation: 在一个实施例中，本发明包括一种用于确定频率控制指令是否会使第一电容器组达到限制并且使用校准值在第一方向上调整第一电容器组并在第二电容器组中调整第二电容器组的方法 方向如果第一个电容器组达到极限。 此外，可以根据其他实施例来计算和存储校准值。 以这种方式，可以实现电容的小的变化和相应的小的频率变化。

公开(公告)号：US07132888B2

公开(公告)日：2006-11-07

申请号：US10809838

申请日：2004-03-26

Applicant: Arya R. Behzad

Inventor： Arya R. Behzad

IPC: H03F3/45

CPC classification number: H03F1/3211 ,  H01F17/0006 ,  H01F17/0013 ,  H01F2017/0026 ,  H01F2017/0053 ,  H01F2021/125 ,  H01L23/5227 ,  H01L27/0248 ,  H01L27/08 ,  H01L2924/0002 ,  H01L2924/3011 ,  H03B5/364 ,  H03B2201/025 ,  H03B2201/0266 ,  H03D7/161 ,  H03D7/18 ,  H03G1/0029 ,  H03H11/1291 ,  H03J1/0075 ,  H03J3/04 ,  H03J3/08 ,  H03J3/185 ,  H03J2200/10 ,  H03L1/023 ,  H03L7/10 ,  H03L7/23 ,  H01L2924/00

Abstract: An integrated receiver with channel selection and image rejection is substantially implemented on a single CMOS integrated circuit. A receiver front end provides programable attenuation and a programable gain low noise amplifier. LC filters integrated onto the substrate in conjunction with image reject mixers provide image frequency rejection. Filter tuning and inductor Q compensation over temperature are performed on chip. Active filters utilize multi track spiral inductors with shields to increase circuit Q. Frequency planning provides additional image rejection. Local oscillator signal generation methods on chip reduce distortion. A PLL generates needed out of band LO signals. Direct synthesis generates in band LO signals. PLL VCOs are centered automatically. A differential crystal oscillator provides a frequency reference. Differential signal transmission throughout the receiver is used. ESD protection is provided by a pad ring and ESD clamping structure. Shunts utilize a gate boosting at each pin to discharge ESD build up. An IF VGA utilizes distortion cancellation achieved with cross coupled differential pair amplifiers having their Vds dynamically modified in conjunction with current steering of the differential pairs sources.

Abstract translation: 具有通道选择和图像抑制的集成接收器基本上在单个CMOS集成电路上实现。 接收机前端提供可编程衰减和可编程增益低噪声放大器。 与图像抑制混合器一起集成到衬底上的LC滤波器提供图像频率抑制。 过滤器调谐和电感Q补偿温度在芯片上执行。 有源滤波器利用具有屏蔽的多轨螺旋电感器来增加电路Q.频率规划提供额外的图像抑制。 本地振荡器信号产生方法在芯片上减少失真。 PLL产生所需的带外LO信号。 直接合成产生带内LO信号。 PLL VCO自动居中。 差分晶体振荡器提供频率参考。 使用整个接收机的差分信号传输。 ESD保护由衬垫环和ESD夹紧结构提供。 分流器利用每个引脚上的门极升压来放电ESD积聚。 IF VGA利用交叉耦合的差分对放大器实现的失真消除，其具有与差分对源的当前转向结合动态修改的V ds。