公开(公告)号：US10797707B2

公开(公告)日：2020-10-06

申请号：US15741448

申请日：2016-05-10

Applicant: CSMC TECHNOLOGIES FAB2 CO., LTD.

Inventor： Xueyan Wang ,  Ying Yang ,  Jingjia Yu

IPC: H03L7/081 ,  H03L7/08 ,  H03L7/00

Abstract: A delay locked loop detection system (10), the system can be used for detecting the working state of a delay locked loop (400) and comprises: a signal generator (300), which is used for generating a reference clock and providing the reference clock to the delay locked loop (400); and a testing instrument (500), which is used for acquiring the clock signals output from the delay locked loop (400) and measuring whether the time delays thereof are consistent with expectations; the detection system (10) further comprises at least one of the following circuits: a pre-receiving circuit (100), which is used for receiving the reference clock from the signal generator (300) and amplifying and shaping the reference clock and then providing the reference clock to the delay locked loop (400); and a multiphase multiplexing circuit (200), which is used for receiving the clock signals output from the delay locked loop (400) and synthesizing and then providing a plurality of clock signals with different delay to the testing instrument (500). Also included is a delay locked loop detection method. The system and method mentioned above enable an accurate measurement for the delays of the delay locked loop.

公开(公告)号：US10782148B2

公开(公告)日：2020-09-22

申请号：US16673634

申请日：2019-11-04

Applicant: CSMC TECHNOLOGIES FAB2 CO., LTD.

Inventor： Huagang Wu

IPC: G01C25/00 ,  G01C19/56 ,  G01C19/5776

Abstract: A method for correcting the driving amplitude of a gyro sensor, mainly comprises adjusting the size of a driving signal (a preset amplitude value) through feedback of a sensor response amplitude signal (an average amplitude value) in a resonance maintaining time period, so that the response amplitude of the resonance maintaining time period tends to be equal, and a stable resonance amplitude is maintained. Also provided is a system for correcting the driving amplitude of a gyro sensor.

公开(公告)号：US10770572B2

公开(公告)日：2020-09-08

申请号：US16311276

申请日：2017-06-21

Applicant: CSMC TECHNOLOGIES FAB2 CO., LTD.

Inventor： Shukun Qi

IPC: H01L29/739 ,  H01L29/78 ,  H01L29/10 ,  H01L29/417

Abstract: A lateral insulated-gate bipolar transistor and a manufacturing method therefor. The lateral insulated-gate bipolar transistor comprises a substrate, an anode terminal and a cathode terminal on the substrate, and a drift region and a gate electrode located between the anode terminal and the cathode terminal. The anode terminal comprises an N-shaped buffer zone on the substrate, a P well in the N-shaped buffer zone, an N+ zone in the P well, a groove located above the N+ zone and partially encircled by the P well, polycrystalline silicon in the groove, P+ junctions at two sides of the groove, and N+ junctions at two sides of the P+ junctions.

公开(公告)号：US20200266188A1

公开(公告)日：2020-08-20

申请号：US16644462

申请日：2018-08-03

Applicant: CSMC TECHNOLOGIES FAB2 CO., LTD.

Inventor： Guangyang WANG

IPC: H01L27/02 ,  H01L23/60 ,  H01L27/06

Abstract: A high voltage device with self-electrostatic discharge protection. The device comprises: a semiconductor substrate; a first N-well (201), a P-well (202), and a second N-well (209) formed in the semiconductor substrate; a first N+ ion implantation region (203) and a first isolation region (207) formed in the first N-well (201); a second N+ ion implantation region (204) and a P+ ion implantation region (205) adjacent to the second N+ ion implantation region (204) that are formed in the P-well (202); a third N+ ion implantation region (208) formed in the second N-well (209); and a second isolation region (210) formed in the semiconductor substrate, the second isolation region (210) covering a portion of the second N-well (209) and a portion of the P-well (202), wherein the second N+ ion implantation region (203), the P+ ion implantation region (205), and the third N+ ion implantation region (208) constitute an NPN-type BJT, and the electrostatic discharge protection is achieved by means of the BJT.

公开(公告)号：US20200258782A1

公开(公告)日：2020-08-13

申请号：US16643170

申请日：2018-08-31

Applicant: CSMC TECHNOLOGIES FAB2 CO., LTD.

Inventor： Lihui GU ,  Sen ZHANG ,  Congming QI

IPC: H01L21/8249 ,  H01L29/739 ,  H01L29/78 ,  H01L27/06

Abstract: An integrated circuit chip and a manufacturing method therefor, and a gate drive circuit, the integrated circuit chip comprising: a semiconductor substrate (103), a high voltage island (101a) being formed in the semiconductor substrate (103); a high voltage junction terminal (102a), the high voltage junction terminal (102a) surrounding the high voltage island (101a), a depletion type MOS device (N1) being formed on the high voltage junction terminal (102a), a gate electrode and a drain electrode of the depletion type MOS device (N1) being short connected, and a source electrode of the depletion type MOS device (N1) being connected to a high side power supply end (VB) of the integrated circuit chip; and a bipolar transistor (Q1), a collector electrode of the bipolar transistor (Q1) being short connected to the substrate and being connected to a low side power supply end (VCC) of the integrated circuit chip, an emitter of the bipolar transistor (Q1) being connected to a gate electrode of the depletion type MOS device (N1).

公开(公告)号：US10659040B2

公开(公告)日：2020-05-19

申请号：US16328402

申请日：2017-08-22

Applicant: CSMC TECHNOLOGIES FAB2 CO., LTD.

Inventor： Chuan Luo

IPC: H03K17/06 ,  H03K17/687 ,  H03K5/02

Abstract: A clock voltage step-up circuit comprises a first inverter, a second inverter, a third inverter, a PMOS transistor, and a bootstrap capacitor. An input end of the first inverter is used for inputting a first clock signal. An input end of the second inverter is connected to an output end of the first inverter, and an output end of the second inverter outputs a first control signal used for controlling a sampling switch; and after the first control signal passes through a fourth inverter, a fifth inverter and a sixth inverter, a second control signal used for controlling the sampling switch is generated. An input end of the third inverter is connected to a second clock signal, and the first clock signals and the second clock signals are a set of clock signals, every two of which are not overlapped.

公开(公告)号：US20190378912A1

公开(公告)日：2019-12-12

申请号：US16462432

申请日：2018-07-03

Applicant: CSMC TECHNOLOGIES FAB2 CO., LTD.

Inventor： Huajun JIN ,  Guipeng SUN

IPC: H01L29/66 ,  H01L29/78

Abstract: A method for manufacturing a semiconductor device, includes: forming a well region (201) in a semiconductor substrate (200) and forming a channel region (202) in the well region (201), and forming a gate oxide layer (210) and a polysilicon layer (220) on the well region (201); etching a portion of the gate oxide layer (210) and the polysilicon layer (220), and exposing a first opening (221) used for forming a source region and a second opening (223) used for forming a drain region; forming a first dielectric layer (230) and a second dielectric layer (240) on the polysilicon layer (220) and in the first opening (221) and the second opening (223) successively, and forming a source region side wall at a side surface of the first opening (221) and forming a drain region side wall at a side surface of the second opening (223); forming a dielectric oxide layer (250) on the polysilicon layer (220), etching the dielectric oxide layer and retaining the dielectric oxide layer (250) located on the drain region side wall; removing the second dielectric layer (240) in the source region side wall and retaining the first dielectric layer (230) therein.

公开(公告)号：US20190334543A1

公开(公告)日：2019-10-31

申请号：US16344734

申请日：2017-11-03

Applicant: CSMC TECHNOLOGIES FAB2 CO., LTD.

Inventor： Chuan LUO

IPC: H03M1/68

Abstract: A segmented resistor string type digital to analog converter comprises: a most significant bit (MSB) resistor string (104) comprising a high level resistor string, an intermediate level resistor string and a ground level resistor string; a decoding circuit (101), configured to decode an n-bit code of the MSB resistor string (104) and output 2n decoded codes; a logic sequential generation circuit (102), connected to the decoding circuit (101) and configured to perform a logic operation on a middle-position code among the 2n decoded codes and a refresh clock signal in non-overlapping sequences, and output two groups of control signals with completely complementary high level durations; a control signal bootstrap circuit (103), connected to the logic sequential generation circuit (102) and configured to perform bootstrap processing on the control signal, and increase the high level of the control signal to a sum of a power supply voltage and a threshold voltage; and a first switch group (106), connected to the control signal bootstrap circuit (103) and the intermediate level resistor string, where on/off of the first switch group (106) is controlled by the control signal after the bootstrap processing, so as to connect the intermediate level resistor string to the circuit or disconnect the intermediate level resistor string from the circuit.

公开(公告)号：US20190259669A1

公开(公告)日：2019-08-22

申请号：US16329550

申请日：2017-08-31

Applicant: CSMC TECHNOLOGIES FAB2 CO., LTD.

Inventor： Yan GU ,  Shikang CHENG ,  Sen ZHANG

IPC: H01L21/8234 ,  H01L29/08 ,  H01L29/10 ,  H01L29/808 ,  H01L29/78 ,  H01L21/265 ,  H01L29/66 ,  H01L29/45 ,  H01L21/306 ,  H01L29/40 ,  H01L27/06

Abstract: A device integrated with JFET, the device is divided into a JFET region and a power device region, and the device includes: a drain (201) with a first conduction type; and a first conduction type region disposed on a front surface of the drain (201); the JFET region includes: a first well (205) with a second conduction type and formed in the first conduction type region; a second well (207) with a second conduction type and formed in the first conduction type region; a JFET source (212) with the first conduction type; a metal electrode formed on the JFET source (212), which is in contact with the JFET source (212); and a second conduction type buried layer (203) formed under the JFET source (212) and the second well (207).

公开(公告)号：US10340912B2

公开(公告)日：2019-07-02

申请号：US15731768

申请日：2015-09-17

Applicant: CSMC TECHNOLOGIES FAB2 CO., LTD.

Inventor： Yun Gao

IPC: G06F1/24 ,  H03K17/22 ,  G05F3/24 ,  H03K17/687

Abstract: A power on reset circuit, comprising: a threshold level control circuit (120) configured to set threshold level values of power on reset and power off reset; a capacitor charge and discharge circuit (130) configured to output a power on reset signal according to the threshold level values set by the threshold level control circuit; and a current bias circuit (110) configured to provide a reference current not varying with a power supply to the threshold level control circuit (120) and the capacitor charge and discharge circuit (130), comprising: a first reference current output terminal connected to the threshold level control circuit (120); a second reference current output terminal connected to the capacitor charge and discharge circuit (130); and a third reference current output terminal connected to the capacitor charge and discharge circuit (130).