公开(公告)号：US10014392B2

公开(公告)日：2018-07-03

申请号：US15564172

申请日：2016-01-29

Applicant: CSMC TECHNOLOGIES FAB2 CO., LTD.

Inventor： Shukun Qi ,  Guangsheng Zhang ,  Guipeng Sun ,  Sen Zhang

IPC: H01L29/06 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/66681 ,  H01L29/0619 ,  H01L29/063 ,  H01L29/0696 ,  H01L29/42368 ,  H01L29/7816 ,  H01L29/7823 ,  H01L29/7835

Abstract: Provided is a laterally diffused metal-oxide-semiconductor field-effect transistor, comprising a substrate (110), a source (150), a drain (140), a body region (160), a P-type field-limiting ring (135), and a well region on the substrate (110); the well region comprises an inserted well (122), which has P-type doping and is disposed below the drain and connected to the drain; N wells (124) disposed at the two sides of the inserted well (122); a P well (126) disposed next to the N well (124) and connected to the N well (124); a P-type field-limiting ring (135), which is disposed inside the N well (124), is a closed ring-shaped structure, and is located at the periphery below the drain (140); the inserted well (122) extends in its longitudinal direction to the position where it is in contact with said P-type field-limiting ring (135); the source (150) and the body region (160) are disposed inside the P well (126).

公开(公告)号：US10770572B2

公开(公告)日：2020-09-08

申请号：US16311276

申请日：2017-06-21

Applicant: CSMC TECHNOLOGIES FAB2 CO., LTD.

Inventor： Shukun Qi

IPC: H01L29/739 ,  H01L29/78 ,  H01L29/10 ,  H01L29/417

Abstract: A lateral insulated-gate bipolar transistor and a manufacturing method therefor. The lateral insulated-gate bipolar transistor comprises a substrate, an anode terminal and a cathode terminal on the substrate, and a drift region and a gate electrode located between the anode terminal and the cathode terminal. The anode terminal comprises an N-shaped buffer zone on the substrate, a P well in the N-shaped buffer zone, an N+ zone in the P well, a groove located above the N+ zone and partially encircled by the P well, polycrystalline silicon in the groove, P+ junctions at two sides of the groove, and N+ junctions at two sides of the P+ junctions.

公开(公告)号：US11315824B2

公开(公告)日：2022-04-26

申请号：US16483081

申请日：2018-07-03

Applicant: CSMC Technologies FAB2 Co., Ltd.

Inventor： Shukun Qi

IPC: H01L21/762 ,  H01L21/02 ,  H01L21/265 ,  H01L21/3105 ,  H01L21/311 ,  H01L21/32 ,  H01L21/761 ,  H01L29/06

Abstract: A method for manufacturing a trench isolation structure comprising forming a shallow trench having a wider upper section and a narrower lower section in a wafer surface, removing part of the silicon oxide by etching, forming a silicon oxide corner structure at a corner at a top corner of the shallow trench by thermal oxidation, depositing silicon nitride on the wafer surface to cover surfaces of the shallow trench silicon oxide and the silicon oxide corner structure, dry etching the silicon nitride on the shallow trench silicon oxide surface thereby forming masking silicon nitride residues extending into the trench, etching downwards to form a deep trench, forming silicon oxide layers on a side wall and the bottom of the deep trench, depositing polycrystalline silicon in the shallow and deep trenches, removing the silicon nitride, and forming silicon oxide in the shallow trench to cover the polycrystalline silicon.

公开(公告)号：US11127840B2

公开(公告)日：2021-09-21

申请号：US16481576

申请日：2018-07-03

Applicant: CSMC TECHNOLOGIES FAB2 CO., LTD.

Inventor： Shukun Qi ,  Guipeng Sun

IPC: H01L21/763 ,  H01L21/473 ,  H01L29/66 ,  H01L21/02 ,  H01L21/311 ,  H01L21/762

Abstract: Disclosed is a method for manufacturing an isolation structure for LDMOS, the method comprising: forming a first groove on the surface of a wafer; filling the first groove with silicon oxide; removing part of the surface of the silicon oxide within the first groove by means of etching; forming a silicon oxide corner structure at the corner of the top of the first groove by means of thermal oxidation; depositing a nitrogen-containing compound on the surface of the wafer to cover the surface of the silicon oxide within the first groove and the surface of the silicon oxide corner structure; dry-etching the nitrogen-containing compound to remove the nitrogen-containing compound from the surface of the silicon oxide within the first groove, and thereby forming a nitrogen-containing compound side wall residue; with the nitrogen-containing compound side wall residue as a mask, continuing to etch downwards to form a second groove; forming a silicon oxide layer on the side wall and the bottom of the second groove; removing the nitrogen-containing compound side wall residue; and filling the first groove and the second groove with silicon oxide.

公开(公告)号：US10199495B2

公开(公告)日：2019-02-05

申请号：US15766082

申请日：2016-08-18

Applicant: CSMC TECHNOLOGIES FAB2 CO., LTD.

Inventor： Shukun Qi ,  Guipeng Sun

IPC: H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119 ,  H01L29/78 ,  H01L29/08 ,  H01L29/06

Abstract: A laterally diffused metal-oxide semiconductor field-effect transistor, comprising a substrate, a first conductivity type well region, a second conductivity type well region, a drain electrode in the first conductivity type well region, a source electrode and a body region in the second conductivity type well region, and a gate electrode arranged across surfaces of the first conductivity type well region and the second conductivity type well region, and also comprising a floating layer ring arranged on the top of the first conductivity type well region and located between the gate electrode and the drain electrode and a plurality of groove polysilicon electrodes running through the floating layer ring and stretching into the first conductivity type well region.

公开(公告)号：US11088253B2

公开(公告)日：2021-08-10

申请号：US16483396

申请日：2018-07-03

Applicant: CSMC TECHNOLOGIES FAB2 CO., LTD.

Inventor： Shukun Qi

IPC: H01L29/40 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78

Abstract: A gate structure of a semiconductor device, includes: a trench gate and a planar gate including a plurality of polysilicon structures (406) separated from each other; the gate structure of the semiconductor device further includes a well region (503) being adjacent to the trench gate and being disposed under the planar gate; a first conduction type doped region (504) being disposed in the well region (503) and including a plurality of regions separated from each other, wherein each region is disposed under adjacent polysilicon structures (406), and respective regions are electrically connected to the planar gate; and a source (504a) being disposed in the well region (503); wherein the trench gate includes: a silicon oxide filler (202) including a side wall silicon oxide and a bottom silicon oxide; a control gate (402) being located over the trench gate, wherein a side wall of the control gate is enclosed by the side wall silicon oxide, and the control gate (402) is electrically-connected to the planar gate; a shield gate (404) having a single segment structure or a longitudinally arranged multiple segments structure; and an insulation silicon oxide (204) being filled between adjacent control gate and shield gate in vertical direction.

公开(公告)号：US20200013864A1

公开(公告)日：2020-01-09

申请号：US16483396

申请日：2018-07-03

Applicant: CSMC TECHNOLOGIES FAB2 CO., LTD.

Inventor： Shukun Qi

IPC: H01L29/423 ,  H01L29/66 ,  H01L29/40

Abstract: A gate structure of a semiconductor device, includes: a trench gate and a planar gate including a plurality of polysilicon structures (406) separated from each other; the gate structure of the semiconductor device further includes a well region (503) being adjacent to the trench gate and being disposed under the planar gate; a first conduction type doped region (504) being disposed in the well region (503) and including a plurality of regions separated from each other, wherein each region is disposed under adjacent polysilicon structures (406), and respective regions are electrically connected to the planar gate; and a source (504a) being disposed in the well region (503); wherein the trench gate includes: a silicon oxide filler (202) including a side wall silicon oxide and a bottom silicon oxide; a control gate (402) being located over the trench gate, wherein a side wall of the control gate is enclosed by the side wall silicon oxide, and the control gate (402) is electrically-connected to the planar gate; a shield gate (404) having a single segment structure or a longitudinally arranged multiple segments structure; and an insulation silicon oxide (204) being filled between adjacent control gate and shield gate in vertical direction.

公开(公告)号：US10249707B2

公开(公告)日：2019-04-02

申请号：US15564727

申请日：2016-01-29

Applicant: CSMC TECHNOLOGIES FAB2 CO., LTD.

Inventor： Shukun Qi

IPC: H01L29/06 ,  H01L29/78 ,  H01L29/10 ,  H01L29/66

Abstract: A laterally diffused metal oxide semiconductor field-effect transistor, comprising a substrate (110), a source electrode (150), a drain electrode (140), a body region (160), and a well region on the substrate, the well region comprising: an insertion-type well (122) having P-type doping, being arranged below the drain electrode and being connected to the drain electrode; N wells (124), arranged on two sides of the insertion-type well; and P wells (126), arranged next to the N wells and being connected to the N wells; the source electrode and the body region are arranged in the P well.