-
公开(公告)号：US20190094302A1
公开(公告)日：2019-03-28
申请号：US15713178
申请日：2017-09-22
发明人： Vivek Sarda
IPC分类号： G01R31/3185 , G05F1/10 , G01R31/319
摘要： During scan testing a voltage regulator is programmed to supply a first voltage to logic under test during a shift portion of the scan test, a second voltage during a first portion of a capture portion of the scan test and at least a third voltage during a second portion of the capture portion of the scan test. The availability of a programmable voltage regulator during shift and capture portions of scan testing allows a less stressful voltage to be used during a shift portion of the scan test to reduce shift failures and allows various voltages to be used during capture portions of the scan testing as a surrogate for testing at different temperatures and to provide more flexibility in testing margins.
-
公开(公告)号：US10222421B1
公开(公告)日：2019-03-05
申请号：US15896678
申请日：2018-02-14
IPC分类号： G01R31/3185 , G01R31/10 , G01R31/28 , G01R31/3177
摘要： Embodiments are disclosed for systems and methods that include pulsing a clock pin of retention cells included within a scan chain to shift a sequence of logic values into the scan chain, so that successive cells are loaded with opposite logic values. Embodiments also include pulsing a retain pin to retain the logic values, and pulsing the clock pin to shift the sequence of logic values through the chain, so that retained logic values are output from, and logic values opposite to the retained logic values are loaded into, the cells. Embodiments also include pulsing a restore pin to restore the retained logic values, pulsing the clock pin to shift the logic values out of the scan chain, comparing the logic values shifted out of the scan chain with the logic values shifted into the scan chain, and detecting a fault on the retain pin based on said comparison.
-
公开(公告)号：US20190069148A1
公开(公告)日：2019-02-28
申请号：US16178108
申请日：2018-11-01
摘要： A system and method of allowing a network device to receive a customized version of a reference design is disclosed. In one embodiment, many values that may be subject to customization are no longer fixed by the reference design. Rather, the reference design utilizes rewritable non-volatile memory to store a set of customization values that can be changed, based on a customer's preference. The system also includes a configuration tool, which interfaces with the network device. Using vendor-unique commands, the configuration tool is able to initialize this set of customization values to the values requested by the customer. In operation, the reference design is downloaded into the network device. The configuration tool is then used to establish the customized parameters for a particular customer. This process allows the manufacturer to create one reference design, which can be customized without the need to modify the code or recompile the source code.
-
公开(公告)号：US10218387B2
公开(公告)日：2019-02-26
申请号：US15589199
申请日：2017-05-08
发明人： Thomas S. David
摘要： A system and method of utilizing ECC memory to detect software errors and malicious activities is disclosed. In one embodiment, after a pool of memory is freed, every data word in that pool is modified to ensure that an ECC error will occur if any data word in that pool is read again. In another embodiment, the ECC memory controller is used to detect and prevent non-secure applications from accessing secure portions of memory.
-
155.发明申请公开(公告)号：US20190051368A1
公开(公告)日：2019-02-14
申请号：US15676743
申请日：2017-08-14
发明人： Mohamed M. Elsayed
摘要： An apparatus includes a sample-and-hold (S/H) circuit. The S/H circuit includes a first switch coupled to receive an input signal. The first switch is further coupled to a first capacitor. The S/H circuit further includes a buffer coupled to the first switch. In addition, the S/H circuit includes a voltage source coupled to an input of the buffer to apply an offset voltage to the input of the buffer.
-
156.发明申请公开(公告)号：US20190051367A1
公开(公告)日：2019-02-14
申请号：US15676731
申请日：2017-08-14
发明人： Mohamed M. Elsayed
CPC分类号： G11C27/024 , H03K17/161
摘要： An apparatus includes a sample-and-hold (S/H) circuit. The S/H circuit includes a first switch to provide an input signal that is to be sampled, and a second switch coupled to receive the sampled signal. The second switch is further coupled to a capacitor. The S/H circuit further includes at least one native transistor coupled to the second switch and to the capacitor.
-
公开(公告)号：US10177781B2
公开(公告)日：2019-01-08
申请号：US13925781
申请日：2013-06-24
发明人： Louis Nervegna , Bruce Del Signore
摘要： A method includes selectively coupling first and second input nodes of a capacitive bridge to first and second voltages, respectively, and selectively coupling first and second output nodes of the capacitive bridge to first and second output terminals, respectively, during a first phase of a clock cycle. The method further includes selectively coupling the first and second input nodes to the second and first voltages, respectively, and selectively coupling the first and second output nodes to the second and first output terminals, respectively, during a second phase of the clock cycle.
-
公开(公告)号：US20190006991A1
公开(公告)日：2019-01-03
申请号：US15639267
申请日：2017-06-30
发明人： TIAGO MARQUES , JOHN KHOURY
CPC分类号： H03B5/366 , H03B5/04 , H03B5/364 , H03B2200/004 , H03B2200/005 , H03B2200/0068 , H03B2201/0208 , H03B2201/0266
摘要： A crystal driver circuit for driving a crystal to oscillate at a resonant frequency including an amplifier having an input coupled to an amplifier input node and having an output coupled to an amplifier output node, a current source that provides a core bias current to the amplifier, a first tune capacitor coupled between the amplifier output node and a reference node, and a second tune capacitor coupled between the amplifier input node and the reference node. The first tune capacitor has a first capacitance that is greater than a second capacitance of the second tune capacitor by a capacitance offset that reduces frequency shift during operation. The first and second capacitances have a combined capacitance that achieves an oscillating signal having a target frequency.
-
公开(公告)号：US10172105B2
公开(公告)日：2019-01-01
申请号：US15164363
申请日：2016-05-25
发明人： Hendricus de Ruijter , Ping Xiong , Wentao Li
摘要： An apparatus includes a radio frequency (RF) receiver having a multi-bit observation interval. The RF receiver includes a Coordinate Rotation Digital Computer (Cordic) circuit to receive a complex signal derived from RF signals and to generate a phase signal. The RF receiver further includes a timing correlator and frequency offset estimator coupled to receive data derived from a frequency signal derived from the phase signal. The RF receiver in addition includes a Viterbi decoder coupled to provide decoded data derived from the frequency signal.
-
公开(公告)号：US10165516B2
公开(公告)日：2018-12-25
申请号：US15196523
申请日：2016-06-29
发明人： Vitor M. Pereira
摘要： Systems and methods are provided that may be implemented to selectively enable relatively higher data throughput and higher power WiFi bidirectional wireless protocol capability during times of system wireless activity, and to selectively disable the WiFi bidirectional wireless protocol and enable relatively lower data throughput and lower power wireless protocol capability during the absence of such system wireless activity. The systems and methods may be implemented to enable bi-directional wireless communication and/or external activation of a wireless device both during times of wireless device activity and during times in which wireless device activity is absent and/or a wireless device is inactive and not transmitting.
-
-
-
-
-
-
-
-
-
搜索结果
1440 条记录 (耗时 0.032 秒)
