公开(公告)号：US09847798B2

公开(公告)日：2017-12-19

申请号：US14961996

申请日：2015-12-08

Applicant: STMicroelectronics (Alps) SAS ,  STMICROELECTRONICS (GRENOBLE 2) SAS

Inventor： Julien Saade ,  Abdelaziz Goulahsen

IPC: H04L27/00 ,  H04B1/04 ,  G06F13/42 ,  H04L25/49

CPC classification number: H04B1/04 ,  G06F13/4282 ,  H04L25/4908

Abstract: The invention relates to a method for serial data transmission, comprising the steps consisting in computing the running disparity (RD) of a bit stream that is being transmitted; when the running disparity reaches a threshold (T), computing a point disparity on a subsequent frame (S) of the stream; if the point disparity has the same sign as the threshold, inverting the states of the bits of the frame in the transmitted bit stream; and inserting into the transmitted bit stream a polarity bit having a state signalling the inversion.

公开(公告)号：US09811920B2

公开(公告)日：2017-11-07

申请号：US15088923

申请日：2016-04-01

Applicant: STMicroelectronics (Grenoble 2) SAS

Inventor： Mathieu Thivin ,  Maurizio Colombo

IPC: G06K9/00 ,  G06T7/40 ,  G06T7/00 ,  H04N9/04 ,  G06T7/60

CPC classification number: G06T7/90 ,  G06T7/70 ,  H04N9/04 ,  H04N9/045 ,  H04N9/646 ,  H04N9/77

Abstract: A digital image processing circuit processes macro-pixels of a digital image. A gain control parameter of each pixel of the macro-pixel of the digital image is determined based on a location of the pixel in the digital image. Relative pixel positions of the pixels of the macro-pixel are determined, the relative pixel positions representing pixel positions with respect to color grids. A gain value of each pixel of the macro-pixel is determined based on the relative pixel positions. The gain values are modified based on the gain control parameters. The modified gains are applied to the pixels of the macro-pixel.

公开(公告)号：US09793181B2

公开(公告)日：2017-10-17

申请号：US14659051

申请日：2015-03-16

Applicant: STMicroelectronics (Grenoble 2) SAS

Inventor： Vratislav Michal

IPC: H01C10/50 ,  H01L21/66 ,  H01C17/22 ,  H01C17/26

CPC classification number: H01L22/14 ,  H01C17/22 ,  H01C17/26

Abstract: A method for calibrating a resistance value comprises the steps of measuring a value of a reference capacitor, and adjusting a variable resistor based on the measured value of the reference capacitor. The method may more specifically comprise the steps of directing a constant current through the reference capacitor during a reference time interval; after the reference time interval, directing the constant current through the variable resistor; and varying the variable resistor value progressively by varying a control signal until a voltage of the variable resistor reaches a voltage of the reference capacitor.

公开(公告)号：US09786701B2

公开(公告)日：2017-10-10

申请号：US14926454

申请日：2015-10-29

Applicant: STMICROELECTRONICS (RESEARCH & DEVELOPMENT) LIMITED ,  STMICROELECTRONICS (GRENOBLE 2) SAS

Inventor： Pascal Mellot ,  Stuart McLeod ,  Bruce Rae ,  Marc Drader

IPC: H01L31/107 ,  H01L27/144 ,  G01S7/486 ,  G01S7/497 ,  H01L31/0216 ,  H01L27/146 ,  H01L27/148

CPC classification number: H01L27/1443 ,  G01S7/4863 ,  G01S7/4865 ,  G01S7/497 ,  H01L27/1446 ,  H01L27/14623 ,  H01L27/14818 ,  H01L31/02164 ,  H01L31/107

Abstract: A circuit may include an array of single photon avalanche diode (SPAD) cells, each SPAD cell configured to be selectively enabled by an activation signal. The circuit may include a control circuit configured to selectively enable a subset of the array of SPAD cells based on a measured count rate of the array of SPAD cells.

公开(公告)号：US09774333B2

公开(公告)日：2017-09-26

申请号：US14882868

申请日：2015-10-14

Applicant: STMicroelectronics (Grenoble 2) SAS

Inventor： Cedric Tubert

IPC: H03K23/54

CPC classification number: H03K23/542

Abstract: A counter circuit includes a first Johnson counter circuit and a second Johnson counter circuit coupled in cascade. Each Johnson counter circuit includes a clock input, a data input, a first clock data output, a second clock data output and a feedback from the second clock data input to first data input. The clock input of the first Johnson counter circuit is configured to receive an input clock signal. The clock input of the second Johnson counter circuit is connected to the second clock data output of the first Johnson counter circuit. A ripple counter circuit has a clock input and additional clock data outputs. The clock input of the ripple counter circuit is connected to the second clock data output of the preceding Johnson counter circuit.

公开(公告)号：US20170270070A1

公开(公告)日：2017-09-21

申请号：US15608857

申请日：2017-05-30

Applicant: STMicroelectronics (Grenoble 2) SAS ,  STMicroelectronics S.r.l.

Inventor： Daniele Mangano ,  Ignazio Antonino Urzi

IPC: G06F13/40 ,  G06F13/14 ,  G06F15/78

CPC classification number: G06F13/4027 ,  G06F13/14 ,  G06F15/7825 ,  G06F2213/0038 ,  H04Q2213/13399 ,  H04Q2213/399

Abstract: A system, such as a System-on-Chip includes an interface component or PLUG which generates transactions over an IP block, such as an interconnect serving one or more clients via virtual channels. The client or clients are mapped onto the virtual channels via client/virtual channel mappings. The virtual channels are provided as a first set of virtual channels in the interface component which cooperate with a second set of virtual channels in the IP block. First and second client/virtual channel mappings for the first set of virtual channels and the second set of virtual channels are provided. The first and second client/virtual channel mappings are separately programmable and mutually decoupled from one another.

公开(公告)号：US20170256514A1

公开(公告)日：2017-09-07

申请号：US15238921

申请日：2016-08-17

Applicant: STMicroelectronics (Grenoble 2) SAS

Inventor： Eric Saugier

IPC: H01L23/00 ,  H01L21/82 ,  H01L31/02 ,  H01L23/48

CPC classification number: H01L24/17 ,  H01L21/82 ,  H01L23/481 ,  H01L24/81 ,  H01L27/14618 ,  H01L27/14636 ,  H01L27/14638 ,  H01L27/14683 ,  H01L31/02 ,  H01L2924/14

Abstract: Electronic devices are collectively fabricated from a main wafer which includes optical elements and a secondary wafer that are mounted one on top of the other to form a combined wafer. A mounting face of the secondary wafer is mated to a front face of the main wafer in such a manner that recesses within the mounting face of the secondary wafer are aligned over the optical elements. The thickness of the secondary wafer reduced until the recesses are opened to form ring structures with openings at the recesses. The combined wafer is diced to form electronic devices. A base wafer of the main wafer and the secondary wafer are made of a same semiconductor material (for example, silicon).

公开(公告)号：US20170201771A1

公开(公告)日：2017-07-13

申请号：US15223221

申请日：2016-07-29

Applicant: STMICROELECTRONICS (GRENOBLE 2) SAS

Inventor： Marina NICOLAS

IPC: H04N19/895 ,  H04N19/48

CPC classification number: H04N19/895 ,  G06T9/00 ,  H04N19/154 ,  H04N19/186 ,  H04N19/426 ,  H04N19/48

Abstract: A method for compressing a data block including sets of homologous components may include selecting a designated component from the data block, and compressing non-designated components with a measurable loss less than or equal to a threshold. The method may further include compressing the designated component based upon at least a selection of values from among the values of the homologous designated components associated with the data of the block.

公开(公告)号：US09698183B2

公开(公告)日：2017-07-04

申请号：US14744482

申请日：2015-06-19

Applicant: STMicroelectronics (Grenoble 2) SAS ,  STMicroelectronics (Alps) SAS

Inventor： Nicolas Moeneclaey ,  Julien-Marc Roux ,  Jerome Bourgoin

IPC: H04N5/374 ,  H01L27/146 ,  H04N5/378 ,  H04N5/367 ,  H04N17/00 ,  H04N5/3745

CPC classification number: H01L27/14612 ,  H01L27/14643 ,  H04N5/367 ,  H04N5/374 ,  H04N5/3742 ,  H04N5/3745 ,  H04N5/378 ,  H04N17/002

Abstract: A CMOS image sensor including: an array of M×N pixels, the pixels of a same column being connected to a same output track, each pixel including a photodiode, a sense node, a transfer transistor, a reset transistor, and a read circuit; and a test circuit including an assembly of N elementary reference cells respectively connected to the N output tracks of the sensor, each cell including a resistor, a sense node, a transfer transistor, a reset transistor, and a read circuit, the N resistors being series-connected between first and second nodes of application of a reference voltage.

公开(公告)号：US09697161B2

公开(公告)日：2017-07-04

申请号：US14219850

申请日：2014-03-19

Applicant: STMicroelectronics (Grenoble 2) SAS ,  STMicroelectronics S.r.l.

Inventor： Daniele Mangano ,  Ignazio Antonino Urzi

IPC: G06F13/40 ,  G06F13/14 ,  G06F15/78

CPC classification number: G06F13/4027 ,  G06F13/14 ,  G06F15/7825 ,  G06F2213/0038 ,  H04Q2213/13399 ,  H04Q2213/399

Abstract: A system, such as a System-on-Chip includes an interface component or PLUG which generates transactions over an IP block, such as an interconnect serving one or more clients via virtual channels. The client or clients are mapped onto the virtual channels via client/virtual channel mappings. The virtual channels are provided as a first set of virtual channels in the interface component which cooperate with a second set of virtual channels in the IP block. First and second client/virtual channel mappings for the first set of virtual channels and the second set of virtual channels are provided. The first and second client/virtual channel mappings are separately programmable and mutually decoupled from one another.