公开(公告)号：US20230317602A1

公开(公告)日：2023-10-05

申请号：US17710871

申请日：2022-03-31

Applicant: Intel Corporation

Inventor： Sukru YEMENICIOGLU ,  Richard E. SCHENKER ,  Xinning WANG ,  Tahir GHANI

IPC: H01L23/528 ,  H01L27/092 ,  H01L21/8238

CPC classification number: H01L23/528 ,  H01L21/823871 ,  H01L27/092

Abstract: Embodiments described herein may be related to apparatuses, processes, and techniques for providing a metal routing layer zero (M0) track within a circuit structure that had a width that overlaps both PMOS and NMOS within the circuit structure. There may be three M0 routing tracks, with a first of the M0 routing tracks directly over PMOS, a second of the M0 routing tracks directly over NMOS, and a third of the M0 routing tracks over a portion separating PMOS and NMOS and overlapping both PMOS and NMOS. The wide second routing track will allow efficient electrical coupling between a device on the PMOS and a device on the NMOS. Other embodiments may be described and/or claimed.

公开(公告)号：US20230290852A1

公开(公告)日：2023-09-14

申请号：US17694170

申请日：2022-03-14

Applicant: Intel Corporation

Inventor： Dan S. LAVRIC ,  Dax M. CRUM ,  YenTing CHIU ,  David J. TOWNER ,  David N. GOLDSTEIN ,  Tahir GHANI

IPC: H01L29/423 ,  H01L29/786 ,  H01L29/06

CPC classification number: H01L29/42392 ,  H01L29/78696 ,  H01L29/0673 ,  H01L29/785

Abstract: Gate-all-around integrated circuit structures having common metal gates and having gate dielectrics with differentiated dipole layers are described. For example, an integrated circuit structure includes a first vertical arrangement of horizontal nanowires, and a second vertical arrangement of horizontal nanowires. A P-type gate stack is over the first vertical arrangement of horizontal nanowires, the P-type gate stack having a mid-gap to P-type conductive layer over a first gate dielectric including a high-k dielectric layer and a first dipole material layer. An N-type gate stack is over the second vertical arrangement of horizontal nanowires, the N-type gate stack having the mid-gap to P-type conductive layer over a second gate dielectric including the high-k dielectric layer and a second dipole material layer, the second dipole layer different than the first dipole material layer.

公开(公告)号：US20230290844A1

公开(公告)日：2023-09-14

申请号：US17694163

申请日：2022-03-14

Applicant: Intel Corporation

Inventor： Leonard P. GULER ,  Mauro J. KOBRINSKY ,  Ehren MANNEBACH ,  Makram ABD EL QADER ,  Tahir GHANI

IPC: H01L29/417 ,  H01L27/088 ,  H01L29/423 ,  H01L29/06 ,  H01L21/8234

CPC classification number: H01L29/41783 ,  H01L27/0886 ,  H01L29/42392 ,  H01L29/0673 ,  H01L21/823475 ,  H01L29/66439

Abstract: Integrated circuit structures having backside self-aligned penetrating conductive source or drain contacts, and methods of fabricating integrated circuit structures having backside self-aligned penetrating conductive source or drain contacts, are described. For example, an integrated circuit structure includes a sub-fin structure over a vertical stack of horizontal nanowires. An epitaxial source or drain structure is laterally adjacent and coupled to the vertical stack of horizontal nanowires. A conductive source or drain contact is laterally adjacent to the sub-fin structure and extends into the epitaxial source or drain structure. The conductive source or drain contact does not extend around the epitaxial source or drain structure.

公开(公告)号：US20230197854A1

公开(公告)日：2023-06-22

申请号：US17553161

申请日：2021-12-16

Applicant: Intel Corporation

Inventor： Leonard P. GULER ,  Tahir GHANI ,  Charles H. WALLACE ,  Mohit K. HARAN ,  Mohammad HASAN ,  Aryan NAVABI-SHIRAZI ,  Allen B. GARDINER

IPC: H01L29/786 ,  H01L29/78 ,  H01L29/08 ,  H01L21/8234 ,  H01L27/088

CPC classification number: H01L29/78618 ,  H01L21/823418 ,  H01L21/823481 ,  H01L27/088 ,  H01L29/785 ,  H01L29/0847 ,  H01L29/42392

Abstract: Integrated circuit structures having a dielectric anchor and confined epitaxial source or drain structure, and methods of fabricating integrated circuit structures having a dielectric anchor and confined epitaxial source or drain structure, are described. For example, an integrated circuit structure includes a sub-fin in a shallow trench isolation (STI) structure. A plurality of horizontally stacked nanowires is over the sub-fin. A gate dielectric material layer is surrounding the plurality of horizontally stacked nanowires. A gate electrode structure is over the gate dielectric material layer. A confined epitaxial source or drain structure is at an end of the plurality of horizontally stacked nanowires. A dielectric anchor is laterally spaced apart from the plurality of horizontally stacked nanowires and recessed into a first portion of the STI structure, the dielectric anchor having an uppermost surface below an uppermost surface of the confined epitaxial source or drain structure.

公开(公告)号：US20230187517A1

公开(公告)日：2023-06-15

申请号：US17551022

申请日：2021-12-14

Applicant: Intel Corporation

Inventor： Leonard P. GULER ,  Charles H. WALLACE ,  Tahir GHANI

IPC: H01L29/423 ,  H01L29/06 ,  H01L29/786 ,  H01L27/088

CPC classification number: H01L29/42392 ,  H01L29/0673 ,  H01L29/78696 ,  H01L27/088

Abstract: Integrated circuit structures having a dielectric anchor void, and methods of fabricating integrated circuit structures having a dielectric anchor void, are described. For example, an integrated circuit structure includes a sub-fin in a shallow trench isolation (STI) structure. A plurality of horizontally stacked nanowires is over the sub-fin. A gate dielectric material layer is surrounding the horizontally stacked nanowires. A gate electrode structure is over the gate dielectric material layer. A dielectric anchor is laterally spaced apart from the plurality of horizontally stacked nanowires and recessed into a first portion of the STI structure. A second portion of the STI structure on a side of the plurality of horizontally stacked nanowires opposite the dielectric anchor has a trench therein. A dielectric gate plug is on the dielectric anchor.

公开(公告)号：US20230187441A1

公开(公告)日：2023-06-15

申请号：US17548027

申请日：2021-12-10

Applicant: Intel Corporation

Inventor： Leonard P. GULER ,  Tahir GHANI ,  Charles H. WALLACE ,  Mohit K. HARAN ,  Sukru YEMENICIOGLU ,  Chanaka D. MUNASINGHE

IPC: H01L27/088 ,  H01L29/06 ,  H01L29/78

CPC classification number: H01L27/0886 ,  H01L29/0669 ,  H01L29/785

Abstract: Integrated circuit structures having trench contact flyover structures, and methods of fabricating integrated circuit structures having trench contact flyover structures, are described. For example, an integrated circuit structure includes a plurality of horizontally stacked nanowires. A gate dielectric material layer is surrounding the plurality of horizontally stacked nanowires. A gate electrode structure is over the gate dielectric material layer. An epitaxial source or drain structure is at an end of the plurality of horizontally stacked nanowires. A conductive trench contact structure is vertically over the epitaxial source or drain structure, the conductive trench contact structure electrically isolated from the epitaxial source or drain structure.

公开(公告)号：US20230187356A1

公开(公告)日：2023-06-15

申请号：US17548006

申请日：2021-12-10

Applicant: Intel Corporation

Inventor： Sukru YEMENICIOUGLU ,  Leonard P. GULER ,  Gilbert DEWEY ,  Tahir GHANI

IPC: H01L23/535 ,  H01L29/06 ,  H01L29/165 ,  H01L29/423 ,  H01L29/775 ,  H01L29/78 ,  H01L29/786 ,  H01L21/02 ,  H01L29/66

CPC classification number: H01L23/535 ,  H01L29/0673 ,  H01L29/165 ,  H01L29/42392 ,  H01L29/775 ,  H01L29/7848 ,  H01L29/78618 ,  H01L29/78696 ,  H01L21/02603 ,  H01L21/02532 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66742

Abstract: Jumper gates for advanced integrated circuit structures are described. For example, an integrated circuit structure includes a first vertical stack of horizontal nanowire segments. A second vertical stack of horizontal nanowire segments is spaced apart from the first vertical stack of horizontal nanowire segments. A conductive structure is laterally between and in direct electrical contact with the first vertical stack of horizontal nanowire segments and with the second vertical stack of horizontal nanowire segments. A first source or drain structure is coupled to the first vertical stack of horizontal nanowire segments at a side opposite the conductive structure. A second source or drain structure is coupled to the second vertical stack of horizontal nanowire segments at a side opposite the conductive structure.

公开(公告)号：US20230089815A1

公开(公告)日：2023-03-23

申请号：US17993438

申请日：2022-11-23

Applicant: Intel Corporation

Inventor： Leonard GULER ,  Nick LINDERT ,  Biswajeet GUHA ,  Swaminathan SIVAKUMAR ,  Tahir GHANI

IPC: H01L29/78 ,  H01L29/417 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/66 ,  H01L29/06 ,  H01L21/762 ,  H01L21/02

Abstract: Fin trim plug structures for imparting channel stress are described. In an example, an integrated circuit structure includes a fin including silicon, the fin having a top and sidewalls. The fin has a trench separating a first fin portion and a second fin portion. A first gate structure including a gate electrode is over the top of and laterally adjacent to the sidewalls of the first fin portion. A second gate structure including a gate electrode is over the top of and laterally adjacent to the sidewalls of the second fin portion. An isolation structure is in the trench of the fin, the isolation structure between the first gate structure and the second gate structure. The isolation structure includes a first dielectric material laterally surrounding a recessed second dielectric material distinct from the first dielectric material, the recessed second dielectric material laterally surrounding an oxidation catalyst layer.

公开(公告)号：US20220399336A1

公开(公告)日：2022-12-15

申请号：US17347979

申请日：2021-06-15

Applicant: Intel Corporation

Inventor： Leonard P. GULER ,  Biswajeet GUHA ,  Tahir GHANI ,  Tsuan-Chung CHANG ,  Sean PURSEL

IPC: H01L27/092 ,  H01L29/06 ,  H01L29/78 ,  H01L29/66 ,  H01L21/8234

Abstract: Fin cuts in neighboring gate and source or drain regions for advanced integrated circuit structure fabrication is described. For example, an integrated circuit structure includes a horizontal stack of semiconductor nanowire portions. A dielectric gate spacer is vertically over the horizontal stack of semiconductor nanowire portions. A gate isolation structure is laterally adjacent to a first side of the horizontal stack of semiconductor nanowire portions. A source or drain isolation structure is laterally adjacent to a second side of the horizontal stack of semiconductor nanowire portions.

公开(公告)号：US20220399233A1

公开(公告)日：2022-12-15

申请号：US17346964

申请日：2021-06-14

Applicant: Intel Corporation

Inventor： Leonard P. GULER ,  Charles H. WALLACE ,  Tahir GHANI

IPC: H01L21/768 ,  H01L23/522 ,  H01L29/66

Abstract: Embodiments disclosed herein include integrated circuit structures and methods of forming such structures. In an embodiment, an integrated circuit structure comprises plurality of gate structures above a substrate, a plurality of conductive trench contact structures alternating with the plurality of gate structures, a plurality of dielectric spacers, a corresponding one of the plurality of dielectric spacers between adjacent ones of the plurality of gate structures and the plurality of conductive trench contact structures, and a plurality of conductive vias, individual ones of the plurality of conductive vias on corresponding ones of the plurality of conductive trench contact structures, wherein bottommost surfaces of the conductive vias are below topmost surfaces of the plurality of conductive trench contact structures.