公开(公告)号：US20200091231A1

公开(公告)日：2020-03-19

申请号：US16685194

申请日：2019-11-15

Applicant: International Business Machines Corporation

Inventor： Takashi Ando ,  Choonghyun Lee

IPC: H01L27/24 ,  H01L45/00

Abstract: Embodiments of the invention are directed to a vertical resistive device. A non-limiting example of the vertical resistive device includes a conductive horizontal electrode, an opening extending through the horizontal electrode, a filament region positioned within the opening and communicatively coupled to a sidewall of the horizontal electrode, and a conductive vertical electrode positioned within the opening and communicatively coupled to the filament region. The vertical electrode includes a first conductive alloy material. Oxygen vacancy formation in the filament region is controlled by the first conductive alloy material of the vertical electrode. A room temperature resistivity of the first conductive alloy material is below about 5×10−8 ohm meters and controlled by at least one of the metals that form the first conductive alloy material.

公开(公告)号：US20200083328A1

公开(公告)日：2020-03-12

申请号：US16125311

申请日：2018-09-07

Applicant: International Business Machines Corporation

Inventor： Juntao Li ,  Kangguo Cheng ,  Choonghyun Lee

IPC: H01L29/06 ,  H01L29/16 ,  H01L29/45 ,  H01L21/02 ,  H01L21/324 ,  H01L21/306 ,  H01L21/311 ,  H01L21/283

Abstract: Stacked SiGe nanotubes and techniques for the fabrication thereof are provided. In one aspect, a method of forming a SiGe nanotube stack includes: forming Si and SiGe layers on a wafer, one on top of another, in an alternating manner; patterning at least one fin in the Si and SiGe layers; depositing an oxide material onto the at least one fin; and annealing the at least one fin under conditions sufficient to diffuse Ge atoms from the SiGe layers along an interface between the oxide material and the Si and SiGe layers to form at least one vertical stack of SiGe nanotubes surrounding Si cores. A SiGe nanotube device and method for formation thereof are also provided.

公开(公告)号：US20200075747A1

公开(公告)日：2020-03-05

申请号：US16679427

申请日：2019-11-11

Applicant: International Business Machines Corporation

Inventor： Choonghyun Lee ,  Kangguo Cheng ,  Juntao Li ,  Shogo Mochizuki

IPC: H01L29/66 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/306 ,  H01L21/225 ,  H01L29/08

Abstract: Methods of fabrication and semiconductor structures includes vertical transport field effect transistors (VTFETs) including a top source/drain extension formed with a sacrificial doped layer. The sacrificial doped layer provides the doping source to form the extension and protects the top of the fin during fabrication so as to prevent thinning, among other advantages.

公开(公告)号：US20200066864A1

公开(公告)日：2020-02-27

申请号：US16110785

申请日：2018-08-23

Applicant: International Business Machines Corporation

Inventor： Takashi Ando ,  Choonghyun Lee ,  SangHoon Shin ,  Jingyun Zhang ,  Pouya Hashemi ,  Alexander Reznicek

IPC: H01L29/51 ,  H01L27/092 ,  H01L29/786 ,  H01L21/8238

Abstract: Vertical transport field effect transistors (FETs) having improved device performance are provided. Notably, vertical transport FETs having a gradient threshold voltage are provided. The gradient threshold voltage is provided by forming a gradient threshold voltage adjusting gate dielectric structure between the bottom drain region of the FET and the top source region of the FET. The gradient threshold voltage adjusting gate dielectric structure includes a doped interface high-k gate dielectric material that is located in proximity to the bottom drain region and a non-doped high-k dielectric material that is located in proximity to the top source region. The non-doped high-k dielectric material has a higher threshold voltage than the doped interface high-k gate dielectric.

公开(公告)号：US20200058753A1

公开(公告)日：2020-02-20

申请号：US16662907

申请日：2019-10-24

Applicant: International Business Machines Corporation

Inventor： Choonghyun Lee ,  Takashi Ando ,  Jingyun Zhang ,  Pouya Hashemi ,  Alexander Reznicek

IPC: H01L29/49 ,  H01L29/66 ,  H01L29/417 ,  H01L27/088 ,  H01L29/78 ,  H01L21/8238 ,  H01L27/092 ,  H01L27/12 ,  H01L21/84 ,  H01L21/8234 ,  H01L23/535 ,  H01L21/3215 ,  H01L21/28 ,  H01L29/08

Abstract: Vertical transport field effect transistors (FETs) having improved device performance are provided. Notably, vertical transport FETs having a gradient threshold voltage are provided. The gradient threshold voltage is provided by introducing a threshold voltage modifying dopant into a physically exposed portion of a metal gate layer composed of an n-type workfunction TiN. The threshold voltage modifying dopant changes the threshold voltage of the original metal gate layer.

公开(公告)号：US20200052124A1

公开(公告)日：2020-02-13

申请号：US16059101

申请日：2018-08-09

Applicant: International Business Machines Corporation

Inventor： Xin Miao ,  Alexander Reznicek ,  Choonghyun Lee ,  Jingyun Zhang

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/66 ,  H01L21/8234 ,  H01L23/532

Abstract: A sacrificial inner dielectric spacer is formed on physically exposed sidewalls of each recessed semiconductor channel material nanosheet of a nanosheet material stack that further includes recessed sacrificial semiconductor material nanosheets that have an inner dielectric spacer formed on physically exposed sidewalls thereof. A local isolation region is then formed by selective epitaxial growth on a surface of a semiconductor substrate containing the nanosheet material stack. After forming the local isolation region, the sacrificial inner dielectric spacers are removed and a source/drain region is formed on the physically exposed surface of each recessed semiconductor channel material nanosheet. A portion of the source/drain structure is formed in a gap located between each neighboring pair of vertically spaced apart inner dielectric spacers.

公开(公告)号：US10559692B2

公开(公告)日：2020-02-11

申请号：US16560607

申请日：2019-09-04

Applicant: International Business Machines Corporation

Inventor： Alexander Reznicek ,  Xin Miao ,  Jingyun Zhang ,  Choonghyun Lee

IPC: H01L29/786 ,  H01L21/8238 ,  H01L27/092 ,  H01L21/02 ,  H01L29/423 ,  H01L29/06 ,  H01L21/762 ,  H01L29/66

Abstract: A thin layer of lattice matched wide bandgap semiconductor material having semi-insulating properties is employed as an isolation layer between the substrate and a vertical stack of suspended semiconductor channel material nanosheets. The presence of such an isolation layer eliminates the parasitic leakage path between the source region and the drain region that typically occurs through the substrate, while not interfering with the CMOS device that is formed around the semiconductor channel material nanosheets.

公开(公告)号：US10559685B2

公开(公告)日：2020-02-11

申请号：US16007263

申请日：2018-06-13

Applicant: International Business Machines Corporation

Inventor： Juntao Li ,  Kangguo Cheng ,  Choonghyun Lee ,  Peng Xu

IPC: H01L21/00 ,  H01L29/78 ,  H01L27/088 ,  H01L29/66 ,  H01L29/08 ,  H01L29/45 ,  H01L21/768 ,  H01L21/8234 ,  H01L27/12 ,  H01L21/8238 ,  H01L21/84 ,  H01L27/092

Abstract: A semiconductor structure and a method for fabricating the same. The semiconductor structure includes a substrate and at least one semiconductor fin contacting the substrate. A first source/drain layer contacts the substrate. A silicide contacts and wraps around the first source/drain layer. The structure also includes a second source/drain layer above the first source/drain layer. The method comprises forming a structure including at least a substrate, a first source/drain layer, and at least one semiconductor fin disposed on and in contact with substrate. A silicide is formed in contact with and wrapping around the first source/drain layer. A gate structure is formed in contact with at least the at least one semiconductor fin. A second source/drain layer is formed above the first source/drain layer.

公开(公告)号：US10559671B2

公开(公告)日：2020-02-11

申请号：US16404704

申请日：2019-05-06

Applicant: International Business Machines Corporation

Inventor： Hemanth Jagannathan ,  Choonghyun Lee ,  Alexander Reznicek ,  Christopher Waskiewicz

IPC: H01L29/66 ,  H01L29/06 ,  H01L29/78

Abstract: A vertical transport field-effect transistor includes a top source/drain region separated from an underlying gate stack by a top spacer including open gaps to reduce capacitance therebetween. Techniques for fabricating the transistor include using a sacrificial spacer that is selectively removed prior to growth of the top source/drain region. The top source/drain region may be confined by opposing dielectric layers.

公开(公告)号：US20200035488A1

公开(公告)日：2020-01-30

申请号：US16589687

申请日：2019-10-01

Applicant: International Business Machines Corporation

Inventor： Juntao Li ,  Kangguo Cheng ,  Peng Xu ,  Choonghyun Lee

IPC: H01L21/02 ,  H01L29/66 ,  H01L29/786 ,  H01L29/423 ,  H01L21/3065 ,  H01L29/06 ,  H01L21/306

Abstract: A method of forming a semiconductor structure includes forming one or more fins disposed on a substrate, rounding surfaces of the one or more fins, forming faceted sidewalk from the rounded surfaces of the one or more fins, and forming a lateral semiconductor nanotube shell on the faceted sidewalk. The lateral semiconductor nanotube shell comprises a hexagonal shape.