公开(公告)号：US11769551B2

公开(公告)日：2023-09-26

申请号：US17399853

申请日：2021-08-11

Applicant: Micron Technology, Inc.

Inventor： Andrea Redaelli ,  Innocenzo Tortorelli ,  Agostino Pirovano ,  Fabio Pellizzer

IPC: G11C11/56 ,  G11C13/00 ,  G11C11/402 ,  G11C11/4074 ,  G11C27/00 ,  G11C7/00 ,  H01L45/00 ,  H10N70/20 ,  H10N70/00

CPC classification number: G11C11/5678 ,  G11C13/004 ,  G11C13/0004 ,  G11C13/0069 ,  H10N70/24 ,  H10N70/826 ,  H10N70/882 ,  G11C13/0002 ,  G11C13/0007 ,  G11C2013/0052 ,  G11C2013/0092 ,  G11C2213/30 ,  G11C2213/31 ,  G11C2213/71

Abstract: Methods, systems, and devices related to a multi-level self-selecting memory device are described. A self-selecting memory cell may store one or more bits of data represented by different threshold voltages of the self-selecting memory cell. A programming pulse may be varied to establish the different threshold voltages by modifying one or more durations during which a fixed level of voltage or fixed level of current is maintained across the self-selecting memory cell. The self-selecting memory cell may include a chalcogenide alloy. A non-uniform distribution of an element in the chalcogenide alloy may determine a particular threshold voltage of the self-selecting memory cell. The shape of the programming pulse may be configured to modify a distribution of the element in the chalcogenide alloy based on a desired logic state of the self-selecting memory cell.

公开(公告)号：US11763886B2

公开(公告)日：2023-09-19

申请号：US17499290

申请日：2021-10-12

Applicant: Micron Technology, Inc.

Inventor： Innocenzo Tortorelli ,  Andrea Redaelli ,  Agostino Pirovano ,  Fabio Pellizzer ,  Mario Allegra ,  Paolo Fantini

IPC: G11C13/02 ,  G11C11/56 ,  G11C13/00 ,  H10B63/00 ,  H10N70/00

CPC classification number: G11C13/0069 ,  G11C11/5678 ,  G11C13/004 ,  G11C13/0004 ,  G11C13/0038 ,  G11C13/0061 ,  H10B63/80 ,  G11C13/0026 ,  G11C13/0028 ,  G11C2013/0052 ,  G11C2013/0092 ,  G11C2213/30 ,  G11C2213/71 ,  H10N70/841 ,  H10N70/882

Abstract: Methods, systems, and devices related to techniques to access a self-selecting memory device are described. A self-selecting memory cell may store one or more bits of data represented by different threshold voltages of the self-selecting memory cell. A programming pulse may be varied to establish the different threshold voltages by modifying one or more time durations during which a fixed level of voltage or current is maintained across the self-selecting memory cell. The self-selecting memory cell may include a chalcogenide alloy. A non-uniform distribution of an element in the chalcogenide alloy may determine a particular threshold voltage of the self-selecting memory cell. The shape of the programming pulse may be configured to modify a distribution of the element in the chalcogenide alloy based on a desired logic state of the self-selecting memory cell.

公开(公告)号：US20230114966A1

公开(公告)日：2023-04-13

申请号：US17048669

申请日：2020-01-28

Applicant: Micron Technology, Inc.

Inventor： Mattia Boniardi ,  Innocenzo Tortorelli

IPC: G11C27/00 ,  G06N3/08 ,  G06N3/065

Abstract: Methods, systems, and devices for analog storing information are described herein. Such methods, systems and devices are suitable for synaptic weight storage in electronic neuro-biological mimicking architectures. A memory device may include a plurality of memory cells each respective memory cell in the plurality of memory cells with a respective programming sensitivity different from the respective programming sensitivity of other memory cells in the plurality. Memory cells may be provided on different decks of a multi-deck memory array. A storage element material of a respective memory cell may have a thickness and/or a composition different from another thickness or composition of a respective storage element material of another respective memory cell on a different deck in the multi-deck memory array. The memory device may further include reading circuitry configured to analogically read respective information programmed in the respective memory cells and to provide an output based on a combination of the respective information analogically read from the respective memory cells.

公开(公告)号：US11600665B2

公开(公告)日：2023-03-07

申请号：US17069347

申请日：2020-10-13

Applicant: Micron Technology, Inc.

Inventor： Marcello Ravasio ,  Samuele Sciarrillo ,  Fabio Pellizzer ,  Innocenzo Tortorelli ,  Roberto Somaschini ,  Cristina Casellato ,  Riccardo Mottadelli

IPC: H01L45/00 ,  H01L27/24

Abstract: The disclosed technology relates generally to integrated circuit devices, and in particular to cross-point memory arrays and methods for fabricating the same. In one aspect, a method of fabricating cross-point memory arrays comprises forming a memory cell material stack which includes a first active material and a second active material over the first active material, wherein one of the first and second active materials comprises a storage material and the other of the first and second active materials comprises a selector material. The method of fabricating cross-point arrays further comprises patterning the memory cell material stack, which includes etching through at least one of the first and second active materials of the memory cell material stack, forming protective liners on sidewalls of the at least one of the first and second active materials after etching through the one of the first and second active materials, and further etching the memory cell material stack after forming the protective liners on the sidewalls of the one of the first and second active materials.

公开(公告)号：US11587979B2

公开(公告)日：2023-02-21

申请号：US17144669

申请日：2021-01-08

Applicant: Micron Technology, Inc.

Inventor： Fabio Pellizzer ,  Innocenzo Tortorelli ,  Agostino Pirovano ,  Andrea Redaelli

IPC: H01L27/24 ,  H01L45/00 ,  G11C13/00

Abstract: The present disclosure includes three dimensional memory arrays, and methods of processing the same. A number of embodiments include a plurality of conductive lines separated from one other by an insulation material, a plurality of conductive extensions arranged to extend substantially perpendicular to the plurality of conductive lines, and a storage element material formed around each respective one of the plurality of conductive extensions and having two different contacts with each respective one of the plurality of conductive lines, wherein the two different contacts with each respective one of the plurality of conductive lines are at two different ends of that respective conductive line.

公开(公告)号：US11515358B2

公开(公告)日：2022-11-29

申请号：US16863555

申请日：2020-04-30

Applicant: Micron Technology, Inc.

Inventor： Innocenzo Tortorelli ,  Fabio Pellizzer

IPC: H01L27/24 ,  H01L45/00

Abstract: A semiconductor device includes first conductive lines extending in a first direction, second conductive lines extending in a second direction, memory cells disposed between the first conductive lines and the second conductive lines, each memory cell disposed at an intersection of a first conductive line and a second conductive line, and a passive material between the memory cells and at least one of the first conductive lines and the second conductive lines. Related semiconductor devices and electronic devices are disclosed.

公开(公告)号：US11443799B2

公开(公告)日：2022-09-13

申请号：US16436734

申请日：2019-06-10

Applicant: Micron Technology, Inc.

Inventor： Innocenzo Tortorelli ,  Russell L. Meyer ,  Agostino Pirovano ,  Andrea Redaelli ,  Lorenzo Fratin ,  Fabio Pellizzer

IPC: G11C11/34 ,  G11C11/56 ,  G11C13/00

Abstract: Disclosed herein is a memory cell including a memory element and a selector device. Data may be stored in both the memory element and selector device. The memory cell may be programmed by applying write pulses having different polarities and magnitudes. Different polarities of the write pulses may program different logic states into the selector device. Different magnitudes of the write pulses may program different logic states into the memory element. The memory cell may be read by read pulses all having the same polarity. The logic state of the memory cell may be detected by observing different threshold voltages when the read pulses are applied. The different threshold voltages may be responsive to the different polarities and magnitudes of the write pulses.

公开(公告)号：US11430509B2

公开(公告)日：2022-08-30

申请号：US16797432

申请日：2020-02-21

Applicant: Micron Technology, Inc.

Inventor： Innocenzo Tortorelli ,  Hari Giduturi ,  Fabio Pellizzer

IPC: G11C7/00 ,  G11C11/56 ,  G11C29/50 ,  G11C11/4074 ,  G11C11/409

Abstract: Methods, systems, and devices for varying-polarity read operations for polarity-written memory cells are described. Memory cells may be programmed to store different logic values based on applying write voltages of different polarities to the memory cells. A memory device may read the logic values based on applying read voltages to the memory cells, and the polarity of the read voltages may vary such that at least some read voltages have one polarity and at least some read voltages have another polarity. The read voltage polarity may vary randomly or according to a pattern and may be controlled by the memory device or by a host device for the memory device.

公开(公告)号：US11423988B2

公开(公告)日：2022-08-23

申请号：US17005928

申请日：2020-08-28

Applicant: Micron Technology, Inc.

Inventor： Innocenzo Tortorelli ,  Mattia Boniardi ,  Mattia Robustelli

IPC: G11C16/10 ,  G11C16/24 ,  G11C16/08 ,  G11C16/26 ,  G11C11/56

Abstract: Methods, systems, and devices for programming techniques for polarity-based memory cells are described. A memory device may use a first type of write operation to program one or more memory cells to a first state and a second type of write operation to program one or more memory cells to a second state. Additionally or alternatively, a memory device may first attempt to use the first type of write operation to program one or more memory cells, and then may use the second type of write operation if the first attempt is unsuccessful.

公开(公告)号：US11417841B2

公开(公告)日：2022-08-16

申请号：US16539932

申请日：2019-08-13

Applicant: Micron Technology, Inc.

Inventor： Stephen W. Russell ,  Andrea Redaelli ,  Innocenzo Tortorelli ,  Agostino Pirovano ,  Fabio Pellizzer ,  Lorenzo Fratin

IPC: H01L45/00 ,  H01L27/24

Abstract: Methods, systems, and devices for techniques for forming self-aligned memory structures are described. Aspects include etching a layered assembly of materials including a first conductive material and a first sacrificial material to form a first set of channels along a first direction that creates a first set of sections. An insulative material may be deposited within each of the first set of channels and a second sacrificial material may be deposited onto the first set of sections and the insulating material. A second set of channels may be etched into the layered assembly of materials along a second direction that creates a second set of sections, where the second set of channels extend through the first and second sacrificial materials. Insulating material may be deposited in the second set of channels and the sacrificial materials removed leaving a cavity. A memory material may be deposited in the cavity.