公开(公告)号：US20180026136A1

公开(公告)日：2018-01-25

申请号：US15723152

申请日：2017-10-02

Applicant: STMICROELECTRONICS, INC.

Inventor： Pierre Morin ,  Nicolas Loubet

IPC: H01L29/78 ,  H01L27/088 ,  H01L29/66 ,  H01L29/165

CPC classification number: H01L29/7848 ,  H01L27/0886 ,  H01L29/165 ,  H01L29/66795 ,  H01L29/785

Abstract: A semiconductor device may include a substrate, a fin above the substrate and having a channel region therein, and source and drain regions adjacent the channel region to generate shear and normal strain on the channel region. A semiconductor device may include a substrate, a fin above the substrate and having a channel region therein, source and drain regions adjacent the channel region, and a gate over the channel region. The fin may be canted with respect to the source and drain regions to generate shear and normal strain on the channel region.

公开(公告)号：US09831342B2

公开(公告)日：2017-11-28

申请号：US14975534

申请日：2015-12-18

Applicant: STMicroelectronics, Inc.

Inventor： Nicolas Loubet ,  Pierre Morin

IPC: H01L27/088 ,  H01L29/78 ,  H01L29/66 ,  H01L29/10 ,  H01L29/165 ,  H01L29/15 ,  H01L29/16 ,  H01L29/161

CPC classification number: H01L29/7848 ,  H01L29/1054 ,  H01L29/155 ,  H01L29/16 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7851

Abstract: Methods and structures for forming strained-channel finFETs are described. Fin structures for finFETs may be formed in two epitaxial layers that are grown over a bulk substrate. A first thin epitaxial layer may be cut and used to impart strain to an adjacent channel region of the finFET via elastic relaxation. The structures exhibit a preferred design range for increasing induced strain and uniformity of the strain over the fin height.

公开(公告)号：US09806196B2

公开(公告)日：2017-10-31

申请号：US15255862

申请日：2016-09-02

Applicant: STMICROELECTRONICS, INC.

Inventor： Pierre Morin ,  Nicolas Loubet

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/165 ,  H01L27/088

CPC classification number: H01L29/7848 ,  H01L27/0886 ,  H01L29/165 ,  H01L29/66795 ,  H01L29/785

Abstract: A semiconductor device may include a substrate, a fin above the substrate and having a channel region therein, and source and drain regions adjacent the channel region to generate shear and normal strain on the channel region. A semiconductor device may include a substrate, a fin above the substrate and having a channel region therein, source and drain regions adjacent the channel region, and a gate over the channel region. The fin may be canted with respect to the source and drain regions to generate shear and normal strain on the channel region.

公开(公告)号：US09660080B2

公开(公告)日：2017-05-23

申请号：US14194215

申请日：2014-02-28

Applicant: STMicroelectronics, Inc.

Inventor： Pierre Morin ,  Nicolas Loubet

IPC: H01L29/06 ,  H01L29/78 ,  H01L29/66 ,  H01L21/225 ,  H01L29/165 ,  H01L29/16 ,  H01L29/161 ,  H01L29/786 ,  H01L29/10

CPC classification number: H01L27/10879 ,  H01L21/2251 ,  H01L29/0649 ,  H01L29/1054 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/41791 ,  H01L29/4236 ,  H01L29/66772 ,  H01L29/66795 ,  H01L29/7825 ,  H01L29/7838 ,  H01L29/7849 ,  H01L29/785 ,  H01L29/7855 ,  H01L29/78603 ,  H01L29/78654

Abstract: Methods and structures for forming a localized, strained region of a substrate are described. Trenches may be formed at boundaries of a localized region of a substrate. An upper portion of sidewalls at the localized region may be covered with a covering layer, and a lower portion of the sidewalls at the localized region may not be covered. A converting material may be formed in contact with the lower portion of the localized region, and the substrate heated. The heating may introduce a chemical species from the converting material into the lower portion, which creates stress in the localized region. The methods may be used to form strained-channel finFETs.

公开(公告)号：US09633893B2

公开(公告)日：2017-04-25

申请号：US15081749

申请日：2016-03-25

Applicant: International Business Machines Corporation ,  STMicroelectronics, Inc.

Inventor： Nicolas Loubet ,  Qing Liu ,  Shom Ponoth

IPC: H01L21/76 ,  H01L21/762 ,  H01L21/84 ,  H01L21/311

CPC classification number: H01L21/76283 ,  H01L21/31111 ,  H01L21/76232 ,  H01L21/84

Abstract: Isolation trenches are etched through an active silicon layer overlying a buried oxide on a substrate into the substrate, and through any pad dielectric(s) on the active silicon layer. Lateral epitaxial growth of the active silicon layer forms protrusions into the isolation trenches to a lateral distance of at least about 5 nanometers, and portions of the isolation trenches around the protrusions are filled with dielectric. Raised source/drain regions are formed on portions of the active silicon layer including a dielectric. As a result, misaligned contacts passing around edges of the raised source/drain regions remain spaced apart from sidewalls of the substrate in the isolation trenches.

公开(公告)号：US09620507B2

公开(公告)日：2017-04-11

申请号：US13907460

申请日：2013-05-31

Applicant: STMicroelectronics, Inc. ,  International Business Machines Corporation

Inventor： Nicolas Loubet ,  Qing Liu ,  Prasanna Khare ,  Stephane Allegret-Maret ,  Bruce Doris ,  Kangguo Cheng

IPC: H01L27/11 ,  H01L27/092 ,  H01L21/8238 ,  H01L21/84 ,  H01L29/66 ,  H01L29/786

CPC classification number: H01L29/66772 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/84 ,  H01L27/092 ,  H01L27/1104 ,  H01L27/1116 ,  H01L29/78654

Abstract: An improved transistor with channel epitaxial silicon and methods for fabrication thereof. In one aspect, a method for fabricating a transistor includes: forming a gate stack structure on an epitaxial silicon region, a width dimension of the epitaxial silicon region approximating a width dimension of the gate stack structure; encapsulating the epitaxial silicon region under the gate stack structure with sacrificial spacers formed on both sides of the gate stack structure and the epitaxial silicon region; forming a channel of the transistor having a width dimension that approximates that of the epitaxial silicon region and the gate stack structure, the epitaxial silicon region and the gate stack structure formed on the channel of the transistor; removing the sacrificial spacers; and growing a raised epitaxial source and drain from the silicon substrate, with portions of the raised epitaxial source and drain in contact with the epitaxial silicon region.

公开(公告)号：US20170062426A1

公开(公告)日：2017-03-02

申请号：US14833857

申请日：2015-08-24

Applicant: STMicroelectronics, Inc.

Inventor： Nicolas Loubet ,  Pierre Morin ,  Yann Mignot

IPC: H01L27/092 ,  H01L21/02 ,  H01L29/06 ,  H01L21/8238 ,  H01L29/49 ,  H01L29/78 ,  H01L29/165 ,  H01L21/762

CPC classification number: H01L21/823821 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/76224 ,  H01L21/823807 ,  H01L21/823878 ,  H01L27/0922 ,  H01L27/0924 ,  H01L29/0649 ,  H01L29/165 ,  H01L29/41791 ,  H01L29/4916 ,  H01L29/7842 ,  H01L29/785

Abstract: Integrated circuits are disclosed in which the strain properties of adjacent pFETs and nFETs are independently adjustable. The pFETs include compressive-strained SiGe on a silicon substrate, while the nFETs include tensile-strained silicon on a strain-relaxed SiGe substrate. Adjacent n-type and p-type FinFETs are separated by electrically insulating regions formed by a damascene process. During formation of the insulating regions, the SiGe substrate supporting the n-type devices is permitted to relax elastically, thereby limiting defect formation in the crystal lattice of the SiGe substrate.

Abstract translation: 公开了集成电路，其中相邻pFET和nFET的应变特性可独立调节。 pFET在硅衬底上包括压应变SiGe，而nFET在应变弛豫SiGe衬底上包括拉伸应变硅。 相邻的n型和p型FinFET由通过镶嵌工艺形成的电绝缘区域分开。 在形成绝缘区域的过程中，允许支持n型器件的SiGe衬底弹性弛豫，从而限制SiGe衬底的晶格中的缺陷形成。

公开(公告)号：US09466718B2

公开(公告)日：2016-10-11

申请号：US14663843

申请日：2015-03-20

Applicant: STMICROELECTRONICS, INC.

Inventor： Pierre Morin ,  Nicolas Loubet

IPC: H01L27/088 ,  H01L29/78 ,  H01L29/66 ,  H01L29/165

CPC classification number: H01L29/7848 ,  H01L27/0886 ,  H01L29/165 ,  H01L29/66795 ,  H01L29/785

Abstract: A semiconductor device may include a substrate, a fin above the substrate and having a channel region therein, and source and drain regions adjacent the channel region to generate shear and normal strain on the channel region. A semiconductor device may include a substrate, a fin above the substrate and having a channel region therein, source and drain regions adjacent the channel region, and a gate over the channel region. The fin may be canted with respect to the source and drain regions to generate shear and normal strain on the channel region.

Abstract translation: 半导体器件可以包括衬底，在衬底上方具有沟道区域的鳍，以及与沟道区相邻的源区和漏区，以在沟道区上产生剪切和正应变。 半导体器件可以包括衬底，在衬底上方的鳍片，其中具有沟道区域，与沟道区域相邻的源极和漏极区域以及沟道区域上的栅极。 翅片可以相对于源极和漏极区域倾斜以在沟道区域上产生剪切和正常应变。

公开(公告)号：US09461174B2

公开(公告)日：2016-10-04

申请号：US14449192

申请日：2014-08-01

Applicant: STMicroelectronics, Inc. ,  International Business Machines Corporation

Inventor： Nicolas Loubet ,  Hong He ,  James Kuss

IPC: H01L29/78 ,  H01L27/12 ,  H01L29/66

CPC classification number: H01L29/785 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/66795

Abstract: A substrate layer formed of a first semiconductor material includes adjacent first and second regions. Fin structures are formed from the substrate layer in both the first and second regions. At least the side walls of the fin structures in the second region are covered with an epitaxially grown layer of second semiconductor material. A drive in process is performed to convert the fin structures in the second region from the first semiconductor material to the second semiconductor material. The first semiconductor material is, for example, silicon, and the second semiconductor material is, for example, silicon germanium or silicon carbide. The fin structures in the first region are provided for a FinFET of a first (for example, n-channel) conductivity type while the fin structures in the second region are provided for a FinFET of a second (for example, p-channel) conductivity type.

Abstract translation: 由第一半导体材料形成的衬底层包括相邻的第一和第二区域。 翅片结构由第一和第二区域中的基底层形成。 至少第二区域中的翅片结构的侧壁被外延生长的第二半导体材料层覆盖。 执行处理中的驱动以将第二区域中的鳍状结构从第一半导体材料转换成第二半导体材料。 第一半导体材料是例如硅，第二半导体材料是例如硅锗或碳化硅。 第一区域中的鳍结构被提供用于第一（例如，n沟道）导电类型的FinFET，而第二区域中的翅片结构被设置用于具有第二（例如，p沟道）导电性的FinFET 类型。

公开(公告)号：US09349730B2

公开(公告)日：2016-05-24

申请号：US13945415

申请日：2013-07-18

Applicant: GLOBALFOUNDRIES Inc. ,  INTERNATIONAL BUSINESS MACHINES CORPORATION ,  STMICROELECTRONICS, INC.

Inventor： Ajey Poovannummoottil Jacob ,  Kangguo Cheng ,  Bruce B. Doris ,  Nicolas Loubet ,  Prasanna Khare ,  Ramachandra Divakaruni

IPC: H01L21/20 ,  H01L27/088 ,  H01L21/84 ,  H01L27/12 ,  H01L21/02

CPC classification number: H01L27/1211 ,  H01L21/02236 ,  H01L21/02255 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/02612 ,  H01L21/02614 ,  H01L21/0262 ,  H01L21/30604 ,  H01L21/308 ,  H01L21/845 ,  H01L27/0886 ,  H01L27/0924 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/7849 ,  H01L29/785

Abstract: Methods and semiconductor structures formed from the methods are provided which facilitate fabricating semiconductor fin structures. The methods include, for example: providing a wafer with at least one semiconductor fin extending above a substrate; transforming a portion of the semiconductor fin(s) into an isolation layer, the isolation layer separating a semiconductor layer of the semiconductor fin(s) from the substrate; and proceeding with forming a fin device(s) of a first architectural type in a first fin region of the semiconductor fin(s), and a fin device(s) of a second architectural type in a second fin region of the semiconductor fin(s), where the first architectural type and the second architectural type are different fin device architectures.

Abstract translation: 提供了由这些方法形成的方法和半导体结构，其有助于制造半导体鳍结构。 所述方法包括例如：提供具有在衬底上延伸的至少一个半导体鳍片的晶片; 将所述半导体鳍片的一部分转换成隔离层，所述隔离层将所述半导体鳍片的半导体层与所述衬底分离; 并且在半导体鳍片的第一鳍片区域中形成第一结构类型的翅片装置，并且在半导体鳍片的第二鳍片区域中形成第二结构类型的鳍片装置（ s），其中第一架构类型和第二架构类型是不同的fin设备架构。