公开(公告)号：US10283624B1

公开(公告)日：2019-05-07

申请号：US15875485

申请日：2018-01-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kai-Hsuan Lee ,  Bo-Yu Lai ,  Chi-On Chui ,  Cheng-Yu Yang ,  Yen-Ting Chen ,  Sai-Hooi Yeong ,  Feng-Cheng Yang ,  Yen-Ming Chen

IPC: H01L21/00 ,  H01L29/66 ,  H01L29/78 ,  H01L29/08 ,  H01L21/762 ,  H01L21/306 ,  H01L29/417

Abstract: A semiconductor device and a method for forming the same are provided. The method includes forming a gate structure over a fin structure. The method further includes forming first gate spacers on opposite sidewalls of the gate structure. The method further includes forming source/drain features in the fin structure and adjacent to the first gate spacers. The method further includes performing a surface treatment process on top surfaces of the source/drain features and outer sidewalls of the first gate spacers. The method further includes depositing a contact etch stop layer (CESL) over the source/drain features and the first gate spacers. A first portion of the CESL is deposited over the top surfaces of the source/drain features at a first deposition rate. A second portion of the CESL is deposited over the outer sidewalls of the first gate spacers at a second deposition rate.

公开(公告)号：US20190067126A1

公开(公告)日：2019-02-28

申请号：US15966186

申请日：2018-04-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yen-Ting Chen ,  Wei-Yang Lee ,  Feng-Cheng Yang ,  Yen-Ming Chen

IPC: H01L21/8238 ,  H01L21/02 ,  H01L21/311 ,  H01L29/66 ,  H01L29/08 ,  H01L29/161 ,  H01L27/092

Abstract: A fin structure of a FinFET device is formed over a substrate. A first layer is formed over the fin structure. A gate layer is formed over the fin structure and over the first layer. The gate layer is patterned into a gate stack that wraps around the fin structure. A second layer is formed over the first layer and over the gate stack. A first etching process is performed to remove portions of the second layer formed over the fin structure, the first layer serves as an etching-stop layer during the first etching process. A second etching process is performed to remove portions of the first layer to expose a portion of the fin structure. A removal of the portions of the first layer does not substantially affect the second layer. A source/drain region is epitaxially grown on the exposed portion of the fin structure.

公开(公告)号：US10141231B1

公开(公告)日：2018-11-27

申请号：US15688274

申请日：2017-08-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheng-Yu Yang ,  Chia-Ta Yu ,  Kai-Hsuan Lee ,  Sai-Hooi Yeong ,  Feng-Cheng Yang

IPC: H01L21/8238 ,  H01L27/092

Abstract: A method includes forming two fins extending from a substrate, each fin having two source/drain (S/D) regions and a channel region; forming a gate stack engaging each fin at the respective channel region; depositing one or more dielectric layers over top and sidewall surfaces of the gate stack and over top and sidewall surfaces of the S/D regions of the fins; and performing an etching process to the one or more dielectric layers. The etching process simultaneously produces a polymer layer over the top surface of the gate stack, resulting in the top and sidewall surfaces of the S/D regions of the fins being exposed and a majority of the sidewall surface of the gate stack still being covered by the one or more dielectric layers. The method further includes growing one or more epitaxial layers over the top and sidewall surfaces of the S/D regions of the fins.

公开(公告)号：US20180337282A1

公开(公告)日：2018-11-22

申请号：US16046740

申请日：2018-07-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei-Yang Lee ,  Chia-Chun Lan ,  Chia-Ling Chan ,  Feng-Cheng Yang ,  Yen-Ming Chen

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/167 ,  H01L21/311 ,  H01L29/08 ,  H01L27/092 ,  H01L29/161

Abstract: A method for fabricating a semiconductor device includes forming a doped semiconductor layer on a substrate and forming a fin structure disposed on the doped semiconductor layer. The fin structure is doped with a p-type dopant. The method further includes forming a source/drain region within an upper portion of the fin structure and forming a fin sidewall along a lower portion of the fin structure. The fin sidewall has the p-type dopant.

公开(公告)号：US20180166553A1

公开(公告)日：2018-06-14

申请号：US15623539

申请日：2017-06-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei-Yang Lee ,  Feng-Cheng Yang ,  Chung-Te Lin ,  Yen-Ming Chen

IPC: H01L29/49 ,  H01L21/311 ,  H01L21/02 ,  H01L29/66 ,  H01L21/302

Abstract: A method includes forming a gate structure on a substrate, forming a seal spacer covering a sidewall of the gate structure, forming a sacrificial spacer covering a sidewall of the seal spacer, forming source/drain regions sandwiching a channel region that is under the gate structure, and depositing a contact etch stop layer covering a sidewall of the sacrificial spacer. The method further includes removing the sacrificial spacer to form a trench, wherein the trench exposes a sidewall of the contact etch stop layer and the sidewall of the seal spacer, and depositing an inter-layer dielectric layer, wherein the inter-layer dielectric layer caps the trench, thereby defining an air gap inside the trench.

公开(公告)号：US09865595B1

公开(公告)日：2018-01-09

申请号：US15490959

申请日：2017-04-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-Ta Yu ,  Sheng-Chen Wang ,  Cheng-Yu Yang ,  Kai-Hsuan Lee ,  Sai-Hooi Yeong ,  Feng-Cheng Yang ,  Yen-Ming Chen

IPC: H01L21/00 ,  H01L21/338 ,  H01L21/337 ,  H01L29/768 ,  H01L29/80 ,  H01L27/088 ,  H01L21/8234 ,  H01L29/08

CPC classification number: H01L27/0886 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823475 ,  H01L29/0847

Abstract: A FinFET device is provided. The FinFET device includes a plurality of fin structures that protrude upwardly out of a dielectric isolation structure. The FinFET device also includes a plurality of gate structures that partially wrap around the fin structures. The fin structures each extend in a first direction, and the gate structures each extend in a second direction different from the first direction. An epitaxial structure is formed over at least a side surface of each of the fin structures. The epitaxial structure includes: a first epi-layer, a second epi-layer, or a third epi-layer. The epitaxial structure formed over each fin structure is separated from adjacent epitaxial structures by a gap. A silicide layer is formed over each of the epitaxial structures. The silicide layer at least partially fills in the gap. Conductive contacts are formed over the silicide layer.

公开(公告)号：US20170373189A1

公开(公告)日：2017-12-28

申请号：US15684088

申请日：2017-08-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei-Yang Lee ,  Tzu-Hsiang Hsu ,  Ting-Yeh Chen ,  Feng-Cheng Yang

IPC: H01L29/78 ,  H01L29/165 ,  H01L29/161 ,  H01L29/16 ,  H01L29/08 ,  H01L27/11 ,  H01L29/66 ,  H01L21/84

CPC classification number: H01L29/7848 ,  H01L21/845 ,  H01L27/1104 ,  H01L27/1116 ,  H01L29/0847 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/7851

Abstract: A semiconductor structure includes a substrate, first gate structures and second gate structures over the substrate, third epitaxial semiconductor features proximate the first gate structures, and fourth epitaxial semiconductor features proximate the second gate structures. The first gate structures have a greater pitch than the second gate structures. The third and fourth epitaxial semiconductor features are at least partially embedded in the substrate. A first proximity of the third epitaxial semiconductor features to the respective first gate structures is smaller than a second proximity of the fourth epitaxial semiconductor features to the respective second gate structures. In an embodiment, a first depth of the third epitaxial semiconductor features embedded into the substrate is greater than a second depth of the fourth epitaxial semiconductor features embedded into the substrate.

公开(公告)号：US20250169170A1

公开(公告)日：2025-05-22

申请号：US19027407

申请日：2025-01-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yen-Ting Chen ,  Bo-Yu Lai ,  Chien-Wei Lee ,  Hsueh-Chang Sung ,  Wei-Yang Lee ,  Feng-Cheng Yang ,  Yen-Ming Chen

IPC: H10D84/83 ,  H01L21/02 ,  H01L21/3065 ,  H10D30/01 ,  H10D30/62 ,  H10D62/10 ,  H10D62/832 ,  H10D64/01 ,  H10D84/01 ,  H10D84/03

Abstract: A method includes forming a semiconductor fin protruding higher than top surfaces of isolation regions. A top portion of the semiconductor fin is formed of a first semiconductor material. A semiconductor cap layer is formed on a top surface and sidewalls of the semiconductor fin. The semiconductor cap layer is formed of a second semiconductor material different from the first semiconductor material. The method further includes forming a gate stack on the semiconductor cap layer, forming a gate spacer on a sidewall of the gate stack, etching a portion of the semiconductor fin on a side of the gate stack to form a first recess extending into the semiconductor fin, recessing the semiconductor cap layer to form a second recess directly underlying a portion of the gate spacer, and performing an epitaxy to grow an epitaxy region extending into both the first recess and the second recess.

公开(公告)号：US12171091B2

公开(公告)日：2024-12-17

申请号：US18446593

申请日：2023-08-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Yu Hsu ,  Jian-Hao Chen ,  Chia-Wei Chen ,  Shan-Mei Liao ,  Hui-Chi Chen ,  Yu-Chia Liang ,  Shih-Hao Lin ,  Kuei-Lun Lin ,  Kuo-Feng Yu ,  Feng-Cheng Yang ,  Yen-Ming Chen

IPC: H10B10/00

Abstract: A transistor includes a gate structure that has a first gate dielectric layer and a second gate dielectric layer. The first gate dielectric layer is disposed over the substrate. The first gate dielectric layer contains a first type of dielectric material that has a first dielectric constant. The second gate dielectric layer is disposed over the first gate dielectric layer. The second gate dielectric layer contains a second type of dielectric material that has a second dielectric constant. The second dielectric constant is greater than the first dielectric constant. The first dielectric constant and the second dielectric constant are each greater than a dielectric constant of silicon oxide.

公开(公告)号：US12154947B2

公开(公告)日：2024-11-26

申请号：US17705540

申请日：2022-03-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tzu-Hsiang Hsu ,  Ting-Yeh Chen ,  Wei-Yang Lee ,  Feng-Cheng Yang ,  Yen-Ming Chen

IPC: H01L29/08 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/66 ,  H01L29/78

Abstract: A semiconductor structure includes a semiconductor fin disposed over a substrate, a metal gate stack disposed over the semiconductor fin, an epitaxial source/drain (S/D) feature disposed over the semiconductor fin and adjacent to the metal gate stack, and a dielectric feature embedded in the semiconductor fin, where a bottom surface of the epitaxial S/D feature is disposed on a top surface of the dielectric feature, and where sidewalls of the epitaxial S/D feature extend to define sidewalls of the dielectric feature.