公开(公告)号：US20230260849A1

公开(公告)日：2023-08-17

申请号：US18305637

申请日：2023-04-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Guan-Lin Chen ,  Chih-Hao Wang ,  Ching-Wei Tsai ,  Shi Ning Ju ,  Jui-Chien Huang ,  Kuo-Cheng Chiang ,  Kuan-Lun Cheng

IPC: H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786 ,  H01L21/02 ,  H01L21/28

CPC classification number: H01L21/823828 ,  H01L21/02603 ,  H01L21/28123 ,  H01L21/823807 ,  H01L21/823878 ,  H01L27/092 ,  H01L29/0649 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66742 ,  H01L29/78618 ,  H01L29/78696

Abstract: Self-aligned gate cutting techniques for multigate devices are disclosed herein that provide multigate devices having asymmetric metal gate profiles and asymmetric source/drain feature profiles. An exemplary multigate device has a channel layer, a metal gate that wraps a portion of the channel layer, and source/drain features disposed over a substrate. The channel layer extends along a first direction between the source/drain features. A first dielectric fin and a second dielectric fin are disposed over the substrate and configured differently. The channel layer extends along a second direction between the first dielectric fin and the second dielectric fin. The metal gate is disposed between the channel layer and the second dielectric fin. In some embodiments, the first dielectric fin is disposed on a first isolation feature, and the second dielectric fin is disposed on a second isolation feature. The first isolation feature and the second isolation feature are configured differently.

公开(公告)号：US11670723B2

公开(公告)日：2023-06-06

申请号：US17097323

申请日：2020-11-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Mao-Lin Huang ,  Lung-Kun Chu ,  Chung-Wei Hsu ,  Jia-Ni Yu ,  Kuo-Cheng Chiang ,  Kuan-Lun Cheng ,  Chih-Hao Wang

IPC: H01L29/78 ,  H01L27/092 ,  H01L21/02 ,  H01L29/08 ,  H01L29/66 ,  H01L29/786 ,  H01L29/06 ,  H01L29/423 ,  H01L21/28 ,  H01L21/8238

CPC classification number: H01L29/78696 ,  H01L21/0262 ,  H01L21/02236 ,  H01L21/02532 ,  H01L21/02603 ,  H01L21/28185 ,  H01L21/823807 ,  H01L27/092 ,  H01L29/0653 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/66742 ,  H01L29/78618 ,  H01L29/78684

Abstract: A semiconductor device according to the present disclosure includes a fin structure over a substrate, a vertical stack of silicon nanostructures disposed over the fin structure, an isolation structure disposed around the fin structure, a germanium-containing interfacial layer wrapping around each of the vertical stack of silicon nanostructures, a gate dielectric layer wrapping around the germanium-containing interfacial layer, and a gate electrode layer wrapping around the gate dielectric layer.

公开(公告)号：US11670692B2

公开(公告)日：2023-06-06

申请号：US17218503

申请日：2021-03-31

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chung-Wei Hsu ,  Lung-Kun Chu ,  Mao-Lin Huang ,  Jia-Ni Yu ,  Kuo-Cheng Chiang ,  Kuan-Lun Cheng ,  Chih-Hao Wang

IPC: H01L29/417 ,  H01L29/786 ,  H01L29/423 ,  H01L21/8234

CPC classification number: H01L29/41733 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823437 ,  H01L21/823475 ,  H01L29/42392 ,  H01L29/78696

Abstract: A semiconductor device includes power rails in a first interconnect structure on a backside of the semiconductor device. The semiconductor device further includes a gate-all-around (GAA) transistor having multiple channel layers stacked over the first interconnect structure, a gate stack wrapping around each of the multiple channel layers except a bottommost one of the multiple channel layers, and a source/drain feature adjoining the channel layers. The semiconductor device further includes a first conductive via connecting the first interconnect structure to a bottom of the source/drain feature and a dielectric feature isolating the bottommost one of the multiple channel layers from the first conductive via.

公开(公告)号：US11594614B2

公开(公告)日：2023-02-28

申请号：US16834637

申请日：2020-03-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jia-Ni Yu ,  Kuo-Cheng Chiang ,  Lung-Kun Chu ,  Chung-Wei Hsu ,  Chih-Hao Wang ,  Mao-Lin Huang

IPC: H01L21/82 ,  H01L21/84 ,  H01L29/66 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/78

Abstract: Multi-gate devices and methods for fabricating such are disclosed herein. An exemplary method includes forming a gate dielectric layer around first channel layers in a p-type gate region and around second channel layers in an n-type gate region. Sacrificial features are formed between the second channel layers in the n-type gate region. A p-type work function layer is formed over the gate dielectric layer in the p-type gate region and the n-type gate region. After removing the p-type work function layer from the n-type gate region, the sacrificial features are removed from between the second channel layers in the n-type gate region. An n-type work function layer is formed over the gate dielectric layer in the n-type gate region. A metal fill layer is formed over the p-type work function layer in the p-type gate region and the n-type work function layer in the n-type gate region.

公开(公告)号：US20220367703A1

公开(公告)日：2022-11-17

申请号：US17869163

申请日：2022-07-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Cheng Chiang ,  Zhi-Chang Lin ,  Shih-Cheng Chen ,  Chih-Hao Wang ,  Pei-Hsun Wang ,  Lo-Heng Chang ,  Jung-Hung Chang

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/417

Abstract: A semiconductor device and a method of forming the same are provided. A semiconductor device according to the present disclosure includes a first source/drain feature, a second source/drain feature, a first semiconductor channel member and a second semiconductor channel member extending between the first and second source/drain features, and a first dielectric feature and a second dielectric feature each including a first dielectric layer and a second dielectric layer different from the first dielectric layer. The first and second dielectric features are sandwiched between the first and second semiconductor channel members.

公开(公告)号：US20220367457A1

公开(公告)日：2022-11-17

申请号：US17871648

申请日：2022-07-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jia-Chuan You ,  Chia-Hao Chang ,  Kuo-Cheng Chiang ,  Kuan-Lun Cheng ,  Chih-Hao Wang

IPC: H01L27/088 ,  H01L29/786 ,  H01L21/8234 ,  H01L29/423

Abstract: A semiconductor device according to the present disclosure includes a first gate structure and a second gate structure aligned along a direction, a first metal layer disposed over the first gate structure, a second metal layer disposed over the second gate structure, and a gate isolation structure extending between the first gate structure and the second gate structure as well as between the first metal layer and the second metal layer.

公开(公告)号：US20220359309A1

公开(公告)日：2022-11-10

申请号：US17814692

申请日：2022-07-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jin-Aun Ng ,  Kuo-Cheng Chiang ,  Carlos H. Diaz ,  Jean-Pierre Colinge

IPC: H01L21/8238 ,  B82Y40/00 ,  H01L29/66 ,  H01L29/786 ,  H01L29/423 ,  H01L29/775 ,  H01L29/06 ,  H01L27/092 ,  H01L29/16 ,  H01L29/78 ,  B82Y10/00

Abstract: Among other things, one or semiconductor arrangements, and techniques for forming such semiconductor arrangements are provided. For example, one or more silicon and silicon germanium stacks are utilized to form PMOS transistors comprising germanium nanostructure channels and NMOS transistors comprising silicon nanostructure channels. In an example, a first silicon and silicon germanium stack is oxidized to transform silicon to silicon oxide regions, which are removed to form germanium nanostructure channels for PMOS transistors. In another example, silicon and germanium layers within a second silicon and silicon germanium stack are removed to form silicon nanostructure channels for NMOS transistors. PMOS transistors having germanium nanostructure channels and NMOS transistors having silicon nanostructure channels are formed as part of a single fabrication process.

公开(公告)号：US11495687B2

公开(公告)日：2022-11-08

申请号：US17001390

申请日：2020-08-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Liang Chen ,  Chih-Ming Lai ,  Ching-Wei Tsai ,  Charles Chew-Yuen Young ,  Jiann-Tyng Tzeng ,  Kuo-Cheng Chiang ,  Ru-Gun Liu ,  Wei-Hao Wu ,  Yi-Hsiung Lin ,  Chia-Hao Chang ,  Lei-Chun Chou

IPC: H01L29/78 ,  H01L21/768 ,  H01L21/8234 ,  H01L23/48 ,  H01L23/528 ,  H01L27/088 ,  H01L29/66 ,  H01L23/485 ,  H01L21/74 ,  H01L23/538 ,  H01L23/535 ,  H01L29/417

Abstract: The present disclosure describes various non-planar semiconductor devices, such as fin field-effect transistors (finFETs) to provide an example, having one or more metal rail conductors and various methods for fabricating these non-planar semiconductor devices. In some situations, the one or more metal rail conductors can be electrically connected to gate, source, and/or drain regions of these various non-planar semiconductor devices. In these situations, the one or more metal rail conductors can be utilized to electrically connect the gate, the source, and/or the drain regions of various non-planar semiconductor devices to other gate, source, and/or drain regions of various non-planar semiconductor devices and/or other semiconductor devices. However, in other situations, the one or more metal rail conductors can be isolated from the gate, the source, and/or the drain regions these various non-planar semiconductor devices. This isolation prevents electrical connection between the one or more metal rail conductors and the gate, the source, and/or the drain regions these various non-planar semiconductor devices.

公开(公告)号：US20220352329A1

公开(公告)日：2022-11-03

申请号：US17813110

申请日：2022-07-18

Applicant: Taiwan Semiconductor Manufacturing Co, Ltd.

Inventor： Kuo-Cheng Chiang ,  Chi-Wen Liu ,  Ying-Keung Leung

IPC: H01L29/417 ,  H01L29/66 ,  H01L21/8234 ,  H01L21/84 ,  H01L27/092 ,  H01L29/78 ,  H01L21/8238 ,  H01L27/108 ,  H01L27/12 ,  H01L27/088 ,  H01L29/06 ,  H01L29/45

Abstract: A method includes forming a gate stack on a middle portion of s semiconductor fin, and forming a first gate spacer on a sidewall of the gate stack. After the first gate spacer is formed, a template dielectric region is formed to cover the semiconductor fin. The method further includes recessing the template dielectric region. After the recessing, a second gate spacer is formed on the sidewall of the gate stack. The end portion of the semiconductor fin is etched to form a recess in the template dielectric region. A source/drain region is epitaxially grown in the recess.

公开(公告)号：US20220344213A1

公开(公告)日：2022-10-27

申请号：US17238376

申请日：2021-04-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Zhi-Chang Lin ,  Shih-Cheng Chen ,  Kuo-Cheng Chiang ,  Kuan-Ting Pan ,  Jung-Hung Chang ,  Lo-Heng Chang ,  Chien Ning Yao

IPC: H01L21/8234 ,  H01L29/786 ,  H01L29/423

Abstract: The present disclosure describes a semiconductor structure with a dielectric liner. The semiconductor structure includes a substrate and a fin structure on the substrate. The fin structure includes a stacked fin structure, a fin bottom portion below the stacked fin structure, and an isolation layer between the stacked fin structure and the bottom fin portion. The semiconductor structure further includes a dielectric liner in contact with an end of the stacked fin structure and a spacer structure in contact with the dielectric liner.