公开(公告)号：US20110266610A1

公开(公告)日：2011-11-03

申请号：US13180361

申请日：2011-07-11

申请人： Seiichi Aritome

发明人： Seiichi Aritome

IPC分类号： H01L29/788

CPC分类号： H01L21/762 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524

摘要： A memory array comprising transistors having isolated inter-gate dielectric regions with respect to one another. Transistors are formed such that each of the transistors in the array has a charge storage region such as a floating gate, a control gate and an inter-gate dielectric layer therebetween. The inter-gate dielectric layer for each transistor is isolated from the inter-gate dielectric of each of the other transistors in the array.

摘要翻译： 一种存储器阵列，包括相对于彼此具有隔离的栅极间电介质区域的晶体管。 晶体管被形成为使得阵列中的每个晶体管具有电荷存储区域，例如浮置栅极，控制栅极和栅极之间的介电层。 每个晶体管的栅极间电介质层与阵列中的每个其它晶体管的栅极间电介质隔离。

公开(公告)号：US20110249494A1

公开(公告)日：2011-10-13

申请号：US13164813

申请日：2011-06-21

申请人： Seiichi Aritome

发明人： Seiichi Aritome

IPC分类号： G11C16/04 ,  G11C16/26 ,  G11C16/14 ,  G11C16/10

CPC分类号： G11C16/0483 ,  G11C16/10 ,  G11C16/3427 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524

摘要： Multiple select gates in association with non-volatile memory cells are described. Various embodiments include multiple select gate structure, process, and operation and their applicability for memory devices, modules, and systems. In one embodiment a memory array is described. The memory array includes a number of select gates coupled in series to a number of non-volatile memory cells. A first select gate includes a control gate and a floating gate electrically connected together and a second select gate includes a control gate and a floating gate which are electrically separated by a dielectric layer.

摘要翻译： 描述与非易失性存储器单元相关联的多个选择门。 各种实施例包括多个选择栅极结构，工艺和操作及其对存储器件，模块和系统的适用性。 在一个实施例中描述了存储器阵列。 存储器阵列包括多个与多个非易失性存储器单元串联耦合的选择栅极。 第一选择栅极包括电连接在一起的控制栅极和浮置栅极，第二选择栅极包括由电介质层电隔离的控制栅极和浮置栅极。

公开(公告)号：US08000136B2

公开(公告)日：2011-08-16

申请号：US12838646

申请日：2010-07-19

申请人： Seiichi Aritome

发明人： Seiichi Aritome

IPC分类号： G11C11/34

CPC分类号： G11C11/5628 ,  G11C5/04 ,  G11C16/0483 ,  G11C16/3418 ,  G11C16/3427 ,  G11C2211/5641

摘要： Memory arrays and methods of operating such memory arrays are described as having a memory cell operated as a single level cell interposed between and coupled to a select gate and a memory cell operated as a multiple level memory cell. In some embodiments, a memory array is described as including a number of select gates coupled in series to a number of memory cells operated as single level memory cells and a number of memory cells operated as multiple level memory cells, where a first select gate is directly coupled to a first memory cell operated as a single level memory cell interposed between and coupled to the first select gate and a continuous number of memory cells operated as multiple level memory cells.

摘要翻译： 存储器阵列和操作这样的存储器阵列的方法被描述为具有作为单电平单元操作的存储单元，该存储单元被插入并耦合到选择栅极和作为多电平存储单元操作的存储单元。 在一些实施例中，存储器阵列被描述为包括与作为单级存储器单元操作的多个存储器单元和作为多级存储器单元操作的多个存储单元串联耦合的多个选择栅极，其中第一选择栅极为 直接耦合到第一存储器单元，该第一存储器单元被操作为插入在第一选择栅极之间并耦合到第一选择栅极的单层存储器单元，以及作为多级存储单元操作的连续数量的存储单元。

公开(公告)号：US07989288B2

公开(公告)日：2011-08-02

申请号：US12841392

申请日：2010-07-22

申请人： Seiichi Aritome

发明人： Seiichi Aritome

IPC分类号： H01L21/8247

CPC分类号： H01L29/42324 ,  H01L21/28273 ,  H01L27/115 ,  H01L27/11521

摘要： A transistor construction includes a first floating gate having a first conductive or semiconductive surface and a second floating gate having a second conductive or semiconductive surface. A dielectric region is circumferentially surrounded by the first surface. The region is configured to reduce capacitive coupling between the first and second surfaces. Another transistor construction includes a floating gate having a cavity extending completely through the floating gate from a first surface of the floating gate to an opposing second surface of the floating gate. The floating gate otherwise encloses the cavity, which is filled with at least one dielectric. A method includes closing an upper portion of an opening in insulator material with a gate material during the deposition before filling a lower portion with the gate material. The depositing and closing provide an enclosed cavity within the lower portion of the opening.

摘要翻译： 晶体管结构包括具有第一导电或半导体表面的第一浮动栅极和具有第二导电或半导电表面的第二浮栅。 电介质区域被第一表面周向地包围。 该区域被配置为减小第一和第二表面之间的电容耦合。 另一种晶体管结构包括浮置栅极，其具有完全穿过浮置栅极的空腔，从浮动栅极的第一表面延伸到浮动栅极的相对的第二表面。 浮动栅极另外封闭空腔，该空腔填充有至少一个电介质。 一种方法包括在沉积期间用栅极材料封闭绝缘体材料中的开口的上部，然后用栅极材料填充下部。 沉积和关闭在开口的下部提供封闭腔。

公开(公告)号：US07898863B2

公开(公告)日：2011-03-01

申请号：US11832513

申请日：2007-08-01

申请人： Seiichi Aritome

发明人： Seiichi Aritome

IPC分类号： G11C11/34

CPC分类号： G11C16/3427 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/3418

摘要： Various embodiments include methods, apparatus, and systems for reading an adjacent cell of a memory array in an electronic device to determine a threshold voltage value of the adjacent cell, the adjacent cell being adjacent a target cell, and reading the target cell of the memory array using a wordline voltage value based on the threshold voltage value of the adjacent cell. Additional apparatus, systems, and methods are described.

摘要翻译： 各种实施例包括用于读取电子设备中的存储器阵列的相邻单元的方法，装置和系统，以确定相邻单元的阈值电压值，相邻单元与目标单元相邻，以及读取存储器的目标单元 阵列使用基于相邻单元的阈值电压值的字线电压值。 描述了附加装置，系统和方法。

公开(公告)号：US07888728B2

公开(公告)日：2011-02-15

申请号：US12140946

申请日：2008-06-17

申请人： Toshitake Yaegashi ,  Kazuhiro Shimizu ,  Seiichi Aritome

发明人： Toshitake Yaegashi ,  Kazuhiro Shimizu ,  Seiichi Aritome

IPC分类号： H01L29/788

CPC分类号： H01L29/788 ,  G11C16/0416 ,  G11C16/0433 ,  G11C16/0483 ,  H01L27/105 ,  H01L27/11526 ,  H01L27/11529 ,  H01L27/11546 ,  Y10S257/908

摘要： In a non-volatile semiconductor memory device and a method for manufacturing the device, each memory cell and its select Tr have the same gate insulating film as a Vcc Tr. Further, the gate electrodes of a Vpp Tr and Vcc Tr are realized by the use of a first polysilicon layer. A material such as salicide or a metal, which differs from second polysilicon (which forms a control gate layer), may be provided on the first polysilicon layer. With the above features, a non-volatile semiconductor memory device can be manufactured by reduced steps and be operated at high speed in a reliable manner.

摘要翻译： 在非易失性半导体存储器件及其制造方法中，每个存储单元及其选择Tr具有与Vcc Tr相同的栅极绝缘膜。 此外，Vpp Tr和Vcc Tr的栅极通过使用第一多晶硅层来实现。 可以在第一多晶硅层上提供与第二多晶硅（形成控制栅极层）不同的诸如硅化物或金属的材料。 利用上述特征，可以通过减小的步骤制造非易失性半导体存储器件并以可靠的方式高速运行。

公开(公告)号：US20100323480A1

公开(公告)日：2010-12-23

申请号：US12868245

申请日：2010-08-25

申请人： Seiichi Aritome

发明人： Seiichi Aritome

IPC分类号： H01L21/8229

CPC分类号： G11C16/0483 ,  G11C16/10 ,  G11C16/3427 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524

摘要： Multiple select gates in association with non-volatile memory cells are described. Various embodiments include multiple select gate structure, process, and operation and their applicability for memory devices, modules, and systems. In one embodiment a memory array is described. The memory array includes a number of select gates coupled in series to a number of non-volatile memory cells. A first select gate includes a control gate and a floating gate electrically connected together and a second select gate includes a control gate and a floating gate which are electrically separated by a dielectric layer.

摘要翻译： 描述与非易失性存储器单元相关联的多个选择门。 各种实施例包括多个选择栅极结构，工艺和操作及其对存储器件，模块和系统的适用性。 在一个实施例中描述了存储器阵列。 存储器阵列包括多个与多个非易失性存储器单元串联耦合的选择栅极。 第一选择栅极包括电连接在一起的控制栅极和浮置栅极，第二选择栅极包括由电介质层电隔离的控制栅极和浮置栅极。

公开(公告)号：US07853841B2

公开(公告)日：2010-12-14

申请号：US11926713

申请日：2007-10-29

申请人： Seiichi Aritome

发明人： Seiichi Aritome

IPC分类号： G11C29/00

CPC分类号： G11C16/28 ,  G11C16/04 ,  G11C16/0483 ,  G11C16/3445 ,  G11C29/02 ,  G11C29/021 ,  G11C29/028 ,  G11C29/50 ,  G11C29/52

摘要： Embodiments of the present disclosure provide methods, devices, and systems for performing a programming operation on an array of non-volatile memory cells. One method includes programming a number of cells to a number of final data states. The method includes performing, prior to completion of, e.g., finishing, the programming operation, an erase state check on a subset of the number of cells, which were to be programmed to an erased state.

摘要翻译： 本公开的实施例提供了用于在非易失性存储器单元阵列上执行编程操作的方法，装置和系统。 一种方法包括将多个单元编程到多个最终数据状态。 该方法包括在完成例如完成编程操作之前，对要被编程为擦除状态的单元数目的子集执行擦除状态检查。

公开(公告)号：US07843735B2

公开(公告)日：2010-11-30

申请号：US11931763

申请日：2007-10-31

申请人： Seiichi Aritome

发明人： Seiichi Aritome

IPC分类号： G11C16/04

CPC分类号： G11C16/349 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/3418 ,  G11C2211/5641

摘要： Methods, devices, modules, and systems for operating memory cells are taught. A method for operating memory cells includes programming at least one of the memory cells to one of a number of states. The method also includes programming at least another one of the memory cells, which is adjacent to the programmed at least one of the memory cells, to one of a different number of states. The method further includes sensing non-erased states of the memory cell's using at least one common voltage level.

摘要翻译： 教授了用于操作存储器单元的方法，设备，模块和系统。 用于操作存储器单元的方法包括将至少一个存储器单元编程为多个状态之一。 该方法还包括将与编程的至少一个存储器单元相邻的存储单元中的至少另一个编程为不同数量的状态之一。 该方法还包括使用至少一个公共电压电平来感测存储器单元的未擦除状态。

公开(公告)号：US07826265B2

公开(公告)日：2010-11-02

申请号：US12327667

申请日：2008-12-03

申请人： Seiichi Aritome

发明人： Seiichi Aritome

IPC分类号： G11C11/34

CPC分类号： G11C16/10 ,  G11C16/20 ,  G11C16/3445 ,  G11C16/3459

摘要： A memory device includes a memory array including a plurality of cells. The cells are divided into a plurality of subsets. Each subset has at least one associated trim parameter. The trim parameter for each subset is stored in the memory array within the associated subset. Circuitry is operable to program at least a portion of a selected subset using the associated trim parameter. A method for operating a memory device includes storing at least one trim parameter for each of a plurality of subsets of a memory array in the memory device within each of the subsets. At least a portion of a selected subset is programmed based on the at least one trim parameter associated with the selected subset.

摘要翻译： 存储器件包括包括多个单元的存储器阵列。 细胞被分成多个子集。 每个子集具有至少一个相关的修剪参数。 每个子集的修剪参数存储在相关子集内的存储器阵列中。 电路可操作以使用相关的修剪参数对选定子集的至少一部分进行编程。 一种用于操作存储器件的方法包括：将存储器阵列的多个子集中的每一个的至少一个修剪参数存储在每个子集内的存储器件中。 基于与所选择的子集相关联的至少一个修剪参数来编程所选子集的至少一部分。