公开(公告)号：US20100167485A1

公开(公告)日：2010-07-01

申请号：US12722247

申请日：2010-03-11

Applicant: Ching-Ya Wang ,  Chung-Hu Ke ,  Wen-Chin Lee

Inventor： Ching-Ya Wang ,  Chung-Hu Ke ,  Wen-Chin Lee

IPC: H01L21/336 ,  H01L21/3205

CPC classification number: H01L29/7848 ,  H01L21/28518 ,  H01L21/76844 ,  H01L21/7685 ,  H01L29/665 ,  H01L29/66515 ,  H01L29/6659 ,  H01L29/7833

Abstract: A semiconductor structure includes a semiconductor substrate; a gate dielectric over the semiconductor substrate; a gate electrode over the gate dielectric; a source/drain region adjacent the gate dielectric; a silicide region on the source/drain region; a metal layer on top of, and physical contacting, the silicide region; an inter-layer dielectric (ILD) over the metal layer; and a contact opening in the ILD. The metal layer is exposed through the contact opening. The metal layer further extends under the ILD. The semiconductor structure further includes a contact in the contact opening.

Abstract translation: 半导体结构包括半导体衬底; 半导体衬底上的栅极电介质; 位于栅极电介质上的栅电极; 与栅极电介质相邻的源极/漏极区域; 源/漏区上的硅化物区; 硅化物区域的顶部和物理接触处的金属层; 金属层上的层间电介质（ILD）; 和ILD的接触开口。 金属层通过接触开口露出。 金属层进一步在ILD下延伸。 半导体结构还包括接触开口中的接触。

公开(公告)号：US20100167101A1

公开(公告)日：2010-07-01

申请号：US12546004

申请日：2009-08-24

Applicant: Tsung-Hsiung Wang ,  Jing-Pin Pan ,  Wen-Chin Lee ,  Yueh-Wei Lin ,  Ya-Tin Hsu ,  Chung-Liang Chang ,  Chih-Jer Shih

Inventor： Tsung-Hsiung Wang ,  Jing-Pin Pan ,  Wen-Chin Lee ,  Yueh-Wei Lin ,  Ya-Tin Hsu ,  Chung-Liang Chang ,  Chih-Jer Shih

IPC: H01M8/10

CPC classification number: H01M8/1041 ,  C08G73/12 ,  C08J5/2256 ,  C08J2371/12 ,  C08J2400/202 ,  C08L79/085 ,  H01M4/92 ,  H01M8/1023 ,  H01M8/1025 ,  H01M8/1027 ,  H01M8/103 ,  H01M8/1032 ,  H01M8/1048 ,  Y02E60/521

Abstract: Proton exchange membrane compositions having high proton conductivity are provided. The proton exchange membrane composition includes a hyper-branched polymer, wherein the hyper-branched polymer has a DB (degree of branching) of more than 0.5. A polymer with high ion conductivity is distributed uniformly over the hyper-branched polymer, wherein the hyper-branched polymer has a weight ratio equal to or more than 5 wt %, based on the solid content of the proton exchange membrane composition.

Abstract translation: 提供了具有高质子传导性的质子交换膜组合物。 质子交换膜组合物包括超支化聚合物，其中超支化聚合物具有大于0.5的DB（支化度）。 具有高离子电导率的聚合物均匀地分布在超支化聚合物上，其中基于质子交换膜组合物的固体含量，超支化聚合物的重量比等于或大于5重量％。

公开(公告)号：US20100059737A1

公开(公告)日：2010-03-11

申请号：US12205585

申请日：2008-09-05

Applicant: Krishna Kumar Bhuwalka ,  Chin-Ya Wang ,  Ken-Ichi Goto ,  Wen-Chin Lee ,  Carlos H. Diaz

Inventor： Krishna Kumar Bhuwalka ,  Chin-Ya Wang ,  Ken-Ichi Goto ,  Wen-Chin Lee ,  Carlos H. Diaz

IPC: H01L29/15

CPC classification number: H01L29/7391 ,  H01L21/26586

Abstract: A semiconductor device includes a channel region; a gate dielectric over the channel region; a gate electrode over the gate dielectric; and a first source/drain region adjacent the gate dielectric. The first source/drain region is of a first conductivity type. At least one of the channel region and the first source/drain region includes a superlattice structure. The semiconductor device further includes a second source/drain region on an opposite side of the channel region than the first source/drain region. The second source/drain region is of a second conductivity type opposite the first conductivity type. At most, one of the first source/drain region and the second source/drain region comprises an additional superlattice structure.

Abstract translation: 半导体器件包括沟道区; 沟道区上的栅极电介质; 位于栅极电介质上的栅电极; 以及与栅极电介质相邻的第一源极/漏极区域。 第一源极/漏极区域是第一导电类型。 沟道区域和第一源极/漏极区域中的至少一个包括超晶格结构。 所述半导体器件还包括与所述第一源极/漏极区域相比在所述沟道区域的相对侧上的第二源极/漏极区域。 第二源极/漏极区域是与第一导电类型相反的第二导电类型。 最多，第一源极/漏极区域和第二源极/漏极区域中的一个包括附加的超晶格结构。

公开(公告)号：US20090140351A1

公开(公告)日：2009-06-04

申请号：US11948823

申请日：2007-11-30

Applicant: Hong-Nien Lin ,  Chih-Hsin Ko ,  Hung-Wei Chen ,  Wen-Chin Lee

Inventor： Hong-Nien Lin ,  Chih-Hsin Ko ,  Hung-Wei Chen ,  Wen-Chin Lee

IPC: H01L29/78

CPC classification number: H01L29/6656 ,  H01L29/165 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/66537 ,  H01L29/6659 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7834 ,  H01L29/7848

Abstract: A method for forming a semiconductor device includes providing a semiconductor substrate; forming a gate dielectric over the semiconductor substrate; forming a gate electrode over the gate dielectric; forming a slim spacer on sidewalls of the gate dielectric and the gate electrode; forming a silicon carbon (SiC) region adjacent the slim spacer; forming a deep source/drain region comprising at least a portion of the silicon carbon region; blanket forming a metal layer, wherein a first interface between the metal layer and the deep source/drain is higher than a second interface between the gate dielectric and the semiconductor substrate; and annealing the semiconductor device to form a silicide region. Preferably, a horizontal spacing between an inner edge of the silicide region and a respective edge of the gate electrode is preferably less than about 150 Å.

Abstract translation: 一种形成半导体器件的方法包括提供半导体衬底; 在所述半导体衬底上形成栅极电介质; 在所述栅极电介质上形成栅电极; 在所述栅极电介质和所述栅电极的侧壁上形成细长间隔物; 形成邻近细长间隔物的硅碳（SiC）区域; 形成包含所述硅碳区域的至少一部分的深源极/漏极区域; 毯形成金属层，其中金属层和深源极/漏极之间的第一界面高于栅极电介质和半导体衬底之间的第二界面; 并对半导体器件进行退火以形成硅化物区域。 优选地，硅化物区域的内边缘和栅电极的相应边缘之间的水平间隔优选小于约150埃。

公开(公告)号：US07538398B2

公开(公告)日：2009-05-26

申请号：US11766773

申请日：2007-06-21

Applicant: Chung-Hu Ke ,  Ching-Ya Wang ,  Wen-Chin Lee

Inventor： Chung-Hu Ke ,  Ching-Ya Wang ,  Wen-Chin Lee

IPC: H01L29/417

CPC classification number: H01L23/485 ,  H01L21/28518 ,  H01L21/28568 ,  H01L21/76844 ,  H01L21/7685 ,  H01L21/76885 ,  H01L29/456 ,  H01L29/6659 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The present invention discloses a semiconductor source/drain contact structure, which comprises a substrate, a source/drain region disposed in the substrate, at least one non-silicided conductive layer including a barrier layer disposed over and in contact with the source/drain region, and one or more contact hole filling metals disposed over and in contact with the at least one non-silicided conductive layer, wherein a first contact area between the at least one non-silicided conductive layer and the source/drain region is substantially larger than a second contact area between the one or more contact hole filling metals and the at least one non-silicided conductive layer.

Abstract translation: 本发明公开了一种半导体源极/漏极接触结构，其包括衬底，设置在衬底中的源极/漏极区域，至少一个非硅化的导电层，其包括设置在源极/漏极区域之上并与源极/漏极区域接触的阻挡层 以及设置在所述至少一个非硅化物导电层上并与所述至少一个非硅化物导电层接触的一个或多个接触孔填充金属，其中所述至少一个非硅化物导电层和所述源极/漏极区之间的第一接触面积基本上大于 所述一个或多个接触孔填充金属和所述至少一个非硅化物导电层之间的第二接触区域。

公开(公告)号：US20090117695A1

公开(公告)日：2009-05-07

申请号：US12260674

申请日：2008-10-29

Applicant: Chih-Hsin Ko ,  Tzu-Juei Wang ,  Hung-Wei Chen ,  Chung-Hu Ke ,  Wen-Chin Lee

Inventor： Chih-Hsin Ko ,  Tzu-Juei Wang ,  Hung-Wei Chen ,  Chung-Hu Ke ,  Wen-Chin Lee

IPC: H01L21/8249

CPC classification number: H01L21/8249 ,  H01L21/823807 ,  H01L27/0623 ,  H01L29/7843

Abstract: A BiCMOS device with enhanced performance by mechanical uniaxial strain is provided. A first embodiment of the present invention includes an NMOS transistor, a PMOS transistor, and a bipolar transistor formed on different areas of the substrate. A first contact etch stop layer with tensile stress is formed over the NMOS transistor, and a second contact etch stop layer with compressive stress is formed over the PMOS transistor and the bipolar transistor, allowing for an enhancement of each device. Another embodiment has, in addition to the stressed contact etch stop layers, strained channel regions in the PMOS transistor and the NMOS transistor, and a strained base in the BJT.

Abstract translation: 提供了通过机械单轴应变增强性能的BiCMOS器件。 本发明的第一实施例包括形成在衬底的不同区域上的NMOS晶体管，PMOS晶体管和双极晶体管。 具有拉伸应力的第一接触蚀刻停止层形成在NMOS晶体管上，并且在PMOS晶体管和双极晶体管上形成具有压应力的第二接触蚀刻停止层，从而允许每个器件的增强。 除了应力接触蚀刻停止层之外，另一实施例还包括PMOS晶体管和NMOS晶体管中的应变通道区域以及BJT中的应变基极。

公开(公告)号：US20090075442A1

公开(公告)日：2009-03-19

申请号：US11855701

申请日：2007-09-14

Applicant: Chung-Hu Ke ,  Ta-Ming Kuan ,  Chih-Hsin Ho ,  Wen-Chin Lee

Inventor： Chung-Hu Ke ,  Ta-Ming Kuan ,  Chih-Hsin Ho ,  Wen-Chin Lee

IPC: H01L21/8238

CPC classification number: H01L21/823807 ,  H01L29/665 ,  H01L29/7847

Abstract: A semiconductor device and method for manufacturing a tensile strained NMOS and a compressive strained PMOS transistor pair, wherein a stressor material is sacrificial is disclosed. The method provides for a substrate, which includes a source/drain for an NMOS transistor, and a PMOS transistor. A first barrier layer is formed on the substrate and a first stressor material is formed on the first barrier layer. The first barrier layer is selectively removed from the PMOS transistor. The substrate is flash annealed and the remaining first stressor material and barrier layer is removed from the substrate.

Abstract translation: 公开了用于制造拉伸应变NMOS和压缩应变PMOS晶体管对的半导体器件和方法，其中应力源材料是牺牲的。 该方法提供了一种衬底，其包括用于NMOS晶体管的源极/漏极和PMOS晶体管。 在基板上形成第一阻挡层，在第一阻挡层上形成第一应力源材料。 从PMOS晶体管选择性地去除第一势垒层。 衬底被闪光退火，剩余的第一应力材料和阻挡层从衬底上去除。

公开(公告)号：US20080242071A1

公开(公告)日：2008-10-02

申请号：US11745862

申请日：2007-05-08

Applicant: Ching-Ya Wang ,  Wen-Chin Lee ,  Denny Tang

Inventor： Ching-Ya Wang ,  Wen-Chin Lee ,  Denny Tang

IPC: H01L21/3205

CPC classification number: H01L21/28185 ,  H01L21/2822 ,  H01L29/51

Abstract: The present disclosure provides a method of fabricating a semiconductor device. The method includes providing a semiconductor substrate, forming a dielectric layer over the semiconductor substrate, treating the dielectric layer with a carbon containing group, forming a conductive layer over the treated dielectric layer, and patterning and etching the dielectric layer and conductive layer to form a gate structure. The carbon containing group includes an OCH3 or CN species.

Abstract translation: 本公开提供了制造半导体器件的方法。 该方法包括提供半导体衬底，在半导体衬底上形成电介质层，用含碳基团处理电介质层，在经处理的电介质层上形成导电层，以及图案化和蚀刻电介质层和导电层以形成 门结构。 含碳基团包括OCH 3或CN物质。

公开(公告)号：US20080145982A1

公开(公告)日：2008-06-19

申请号：US12036616

申请日：2008-02-25

Applicant: Chih-Hsin KO ,  Wen-Chin Lee ,  Yee-Chia Yeo ,  Chung-Hu Ke

Inventor： Chih-Hsin KO ,  Wen-Chin Lee ,  Yee-Chia Yeo ,  Chung-Hu Ke

IPC: H01L21/00 ,  H01L21/3205

CPC classification number: H01L29/66772 ,  H01L27/1203 ,  H01L29/78618 ,  Y10S257/90

Abstract: A semiconductor device comprises a semiconductor mesa overlying a dielectric layer, a gate stack formed overlying the semiconductor mesa, and an isolation spacer formed surrounding the semiconductor mesa and filling any undercut region at edges of the semiconductor mesa.

公开(公告)号：US07369118B2

公开(公告)日：2008-05-06

申请号：US10996459

申请日：2004-11-26

Applicant: Wen-Chin Lee ,  Hsiang-Kuang Chen

Inventor： Wen-Chin Lee ,  Hsiang-Kuang Chen

IPC: G09G5/08

CPC classification number: G06F3/0362 ,  G06F3/0383

Abstract: A magnetic oscillation metric controller applied to computer peripheral or electronic communication system essentially operating on a scrolling wheel for lateral metric control to provide precise, consistent, reliable and programmable adjustment oscillation sensitivity by driving a permanent magnet to generate signals of changed magnetic fields resulted from displacement; and retrieving the data of changed signals for achieving metric control purpose.

Abstract translation: 应用于计算机外围或电子通信系统的磁振荡度量控制器，其基本上在用于横向度量控制的滚动轮上操作，以通过驱动永久磁体以产生由位移产生的变化的磁场的信号来提供精确，一致，可靠和可编程的调节振荡灵敏度 ; 以及检索改变信号的数据以达到度量控制目的。