Headphone off-ear detection
    161.
    发明授权

    公开(公告)号:US09980034B2

    公开(公告)日:2018-05-22

    申请号:US15792394

    申请日:2017-10-24

    Abstract: Disclosed is a signal processor for headphone off-ear detection. The signal processor includes an audio output to transmit an audio signal toward a headphone speaker in a headphone cup. The signal processor also includes a feedback (FB) microphone input to receive a FB signal from a FB microphone in the headphone cup. The signal processor also includes an off-ear detection (OED) signal processor to determine an audio frequency response of the FB signal over an OED frame as a received frequency response. The OED processor also determines an audio frequency response of the audio signal times an off-ear transfer function between the headphone speaker and the FB microphone as an ideal off-ear response. A difference metric si generated comparing the received frequency response to the ideal off-ear frequency response. The difference metric is employed to detect when the headphone cup is disengaged from an ear.

    HEADPHONE OFF-EAR DETECTION
    163.
    发明申请

    公开(公告)号:US20180115815A1

    公开(公告)日:2018-04-26

    申请号:US15792394

    申请日:2017-10-24

    Abstract: Disclosed is a signal processor for headphone off-ear detection. The signal processor includes an audio output to transmit an audio signal toward a headphone speaker in a headphone cup. The signal processor also includes a feedback (FB) microphone input to receive a FB signal from a FB microphone in the headphone cup. The signal processor also includes an off-ear detection (OED) signal processor to determine an audio frequency response of the FB signal over an OED frame as a received frequency response. The OED processor also determines an audio frequency response of the audio signal times an off-ear transfer function between the headphone speaker and the FB microphone as an ideal off-ear response. A difference metric si generated comparing the received frequency response to the ideal off-ear frequency response. The difference metric is employed to detect when the headphone cup is disengaged from an ear.

    Wide supply range precision startup current source

    公开(公告)号:US09946277B2

    公开(公告)日:2018-04-17

    申请号:US15078894

    申请日:2016-03-23

    CPC classification number: G05F1/468

    Abstract: A start-up circuit for a bandgap reference voltage generator circuit, including a first native transistor with a drain connected to a supply voltage of the bandgap reference voltage generator circuit and a source connected to a gate of the first native transistor; a low voltage transistor with a source connected to ground, a drain connected to the source of the first native transistor, and a gate connected to a resistor; a second native transistor with a source connected to the resistor, a gate connected to the source of the first native transistor; a high voltage transistor with a drain connected to a drain of the second native transistor and a source connected to the supply voltage; and a transistor with a gate connected to the gate of the first high voltage transistor and a drain which provides a start-up current for the bandgap reference voltage generator circuit.

    WIDE SUPPLY RANGE PRECISION STARTUP CURRENT SOURCE

    公开(公告)号:US20170277210A1

    公开(公告)日:2017-09-28

    申请号:US15078894

    申请日:2016-03-23

    CPC classification number: G05F1/468

    Abstract: A start-up circuit for a bandgap reference voltage generator circuit, including a first native transistor with a drain connected to a supply voltage of the bandgap reference voltage generator circuit and a source connected to a gate of the first native transistor; a low voltage transistor with a source connected to ground, a drain connected to the source of the first native transistor, and a gate connected to a resistor; a second native transistor with a source connected to the resistor, a gate connected to the source of the first native transistor; a high voltage transistor with a drain connected to a drain of the second native transistor and a source connected to the supply voltage; and a transistor with a gate connected to the gate of the first high voltage transistor and a drain which provides a start-up current for the bandgap reference voltage generator circuit.

    LOW POWER SYNCHRONOUS DATA INTERFACE
    168.
    发明申请

    公开(公告)号:US20170257702A1

    公开(公告)日:2017-09-07

    申请号:US15599331

    申请日:2017-05-18

    Abstract: A low power, digital audio interface includes support for variable length coding depending on content of the audio data sent from the interface. A particularized coding system is implemented that uses techniques of silence detection, dynamic scaling, and periodic encoding to reduce sent data to a minimum. Other techniques include variable packet scaling based on an audio sample rate. Differential signaling techniques are also used. The digital audio interface may be used in a headphone interface to drive digital headphones. A detector in the interface may detect whether digital or analog headphones are coupled to a headphone jack and drive the headphone jack accordingly.

    SPDIF CLOCK AND DATA RECOVERY WITH SAMPLE RATE CONVERTER

    公开(公告)号:US20170222793A1

    公开(公告)日:2017-08-03

    申请号:US15484408

    申请日:2017-04-11

    CPC classification number: H04L7/033 G06F13/4295 H04L7/0029 H04L7/02

    Abstract: A method can include a digital oversampler oversampling an input data stream, a rate generator selecting a frequency that is not less than an expected frequency of the input data stream, a rate generator clock of the rate generator outputting a clock signal that has the selected frequency, determining whether a sample receiver has received at least one sample of the input data stream from the digital oversampler, and, responsive to a determination that the sample receiver has received at least one sample of the input data stream from the digital oversampler, incrementing a sample counter by each received sample. The method can also include a sample rate converter accumulating samples from the sample receiver at the rate of a “toothless” clock signal, determining whether an output of the sample counter is greater than zero, and, responsive to a determination that the output of the sample counter is greater than zero, an AND gate passing the “toothless” clock signal to the sample rate converter.

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