公开(公告)号：US08012816B2

公开(公告)日：2011-09-06

申请号：US12347925

申请日：2008-12-31

Applicant: Marko Radosavljevic ,  Benjamin Chu-Kung ,  Mantu K. Hudait ,  Ravi Pillarisetty

Inventor： Marko Radosavljevic ,  Benjamin Chu-Kung ,  Mantu K. Hudait ,  Ravi Pillarisetty

IPC: H01L21/338 ,  H01L21/3205 ,  H01L21/4763

CPC classification number: H01L29/0847 ,  B82Y10/00 ,  H01L29/122 ,  H01L29/4236 ,  H01L29/452 ,  H01L29/475 ,  H01L29/517 ,  H01L29/66462 ,  H01L29/7783

Abstract: A quantum well is formed for a deep well III-V semiconductor device using double pass patterning. In one example, the well is formed by forming a first photolithography pattern over terminals on a material stack, etching a well between the terminals using the first photolithography patterning, removing the first photolithography pattern, forming a second photolithography pattern over the terminals and at least a portion of the well, deepening the well between the terminals by etching using the second photolithography pattern, removing the second photolithography pattern, and finishing the terminals and the well to form a device on the material stack.

Abstract translation: 对于使用双向图案化的深阱III-V半导体器件形成量子阱。 在一个示例中，孔通过在材料堆叠上的端子上形成第一光刻图案，使用第一光刻图案蚀刻端子之间的阱，去除第一光刻图案，在端子上形成第二光刻图案，并且至少 通过使用第二光刻图案的蚀刻，去除第二光刻图案，以及完成端子和阱以在材料堆叠上形成器件，从而使端子之间的阱深化，从而使端子之间的阱加深。

公开(公告)号：US20110147795A1

公开(公告)日：2011-06-23

申请号：US12646436

申请日：2009-12-23

Applicant: Willy Rachmady ,  Marko Radosavljevic ,  Gilbert Dewey ,  Robert S. Chau

Inventor： Willy Rachmady ,  Marko Radosavljevic ,  Gilbert Dewey ,  Robert S. Chau

IPC: H01L29/78 ,  H01L21/335

CPC classification number: H01L29/7786 ,  H01L29/2003 ,  H01L29/513 ,  H01L29/66431 ,  H01L29/66462 ,  H01L29/66522 ,  H01L29/78

Abstract: A group III chalcogenide layer for interfacing a high-k dielectric to a III-V semiconductor surface and methods of forming the same. A III-V QWFET includes a gate stack which comprises a high-K gate dielectric layer disposed on an interfacial layer comprising a group III chalcogenide. In an embodiment, a III-V semiconductor surface comprising a native oxide is sequentially exposed to TMA and H2S provided in an ALD process to remove substantially all the native oxide and form an Al2S3 layer on the semiconductor surface.

Abstract translation: 用于将高k电介质与III-V半导体表面接合的III族硫属化物层及其形成方法。 III-V QWFET包括栅极堆叠，其包括设置在包含III族硫族化物的界面层上的高K栅极电介质层。 在一个实施方案中，包含天然氧化物的III-V半导体表面依次暴露于在ALD工艺中提供的TMA和H 2 S以去除基本上所有的天然氧化物并在半导体表面上形成Al 2 S 3层。

公开(公告)号：US20110147713A1

公开(公告)日：2011-06-23

申请号：US12646621

申请日：2009-12-23

Applicant: Ravi Pillarisetty ,  Benjamin Chu-Kung ,  Mantu K. Hudait ,  Marko Radosavljevic ,  Jack T. Kavalieros ,  Willy Rachmady ,  Niloy Mukherjee ,  Robert S. Chau

Inventor： Ravi Pillarisetty ,  Benjamin Chu-Kung ,  Mantu K. Hudait ,  Marko Radosavljevic ,  Jack T. Kavalieros ,  Willy Rachmady ,  Niloy Mukherjee ,  Robert S. Chau

IPC: H01L29/66 ,  H01L21/336 ,  H01L29/78

CPC classification number: H01L29/7784 ,  H01L29/151 ,  H01L29/155 ,  H01L29/201 ,  H01L29/205 ,  H01L29/401 ,  H01L29/41725 ,  H01L29/41775 ,  H01L29/42316 ,  H01L29/4236 ,  H01L29/517 ,  H01L29/66462 ,  H01L29/775 ,  H01L29/7783 ,  H01L29/78

Abstract: Techniques are disclosed for providing a low resistance self-aligned contacts to devices formed in a semiconductor heterostructure. The techniques can be used, for example, for forming contacts to the gate, source and drain regions of a quantum well transistor fabricated in III-V and SiGe/Ge material systems. Unlike conventional contact process flows which result in a relatively large space between the source/drain contacts to gate, the resulting source and drain contacts provided by the techniques described herein are self-aligned, in that each contact is aligned to the gate electrode and isolated therefrom via spacer material.

Abstract translation: 公开了用于向半导体异质结构中形成的器件提供低电阻自对准触点的技术。 这些技术可以用于例如形成与在III-V和SiGe / Ge材料系统中制造的量子阱晶体管的栅极，源极和漏极区的接触。 不同于在源极/漏极接触到栅极之间的相对大的空间的常规接触工艺流程，由本文所描述的技术提供的所得到的源极和漏极触点是自对准的，因为每个触点与栅电极对准并且被隔离 通过间隔材料。

公开(公告)号：US20110147710A1

公开(公告)日：2011-06-23

申请号：US12646408

申请日：2009-12-23

Applicant: Gilbert Dewey ,  Marko Radosavljevic ,  Ravi Pillarisetty ,  Robert S. Chau

Inventor： Gilbert Dewey ,  Marko Radosavljevic ,  Ravi Pillarisetty ,  Robert S. Chau

IPC: H01L29/78 ,  H01L29/12 ,  H01L21/336

CPC classification number: H01L29/7786 ,  H01L29/2003 ,  H01L29/513 ,  H01L29/66431 ,  H01L29/66462

Abstract: Non-silicon metal-insulator-semiconductor (MIS) devices and methods of forming the same. The non-silicon MIS device includes a gate dielectric stack which comprises at least two layers of non-native oxide or nitride material. The first material layer of the gate dielectric forms an interface with the non-silicon semiconductor surface and has a lower dielectric constant than a second material layer of the gate dielectric. In an embodiment, a dual layer including a first metal silicate layer and a second oxide layer provides both a good quality oxide-semiconductor interface and a high effective gate dielectric constant.

Abstract translation: 非硅金属绝缘体半导体（MIS）器件及其形成方法。 非硅MIS器件包括包含至少两层非自然氧化物或氮化物材料的栅极电介质叠层。 栅极电介质的第一材料层与非硅半导体表面形成界面，并且具有比栅极电介质的第二材料层更低的介电常数。 在一个实施例中，包括第一金属硅酸盐层和第二氧化物层的双层提供良好质量的氧化物半导体界面和高有效栅极介电常数。

公开(公告)号：US20110147706A1

公开(公告)日：2011-06-23

申请号：US12646697

申请日：2009-12-23

Applicant: Marko Radosavljevic ,  Gilbert Dewey ,  Niloy Mukherjee ,  Ravi Pillarisetty

Inventor： Marko Radosavljevic ,  Gilbert Dewey ,  Niloy Mukherjee ,  Ravi Pillarisetty

IPC: H01L29/778 ,  H01L21/335

CPC classification number: H01L29/7782 ,  B82Y10/00 ,  H01L29/66431 ,  H01L29/66462 ,  H01L29/7783 ,  H01L29/7848

Abstract: Embodiments of the present disclosure describe techniques and configurations to impart strain to integrated circuit devices such as horizontal field effect transistors. An integrated circuit device includes a semiconductor substrate, a first barrier layer coupled with the semiconductor substrate, a quantum well channel coupled to the first barrier layer, the quantum well channel comprising a first material having a first lattice constant, and a source structure coupled to the quantum well channel, the source structure comprising a second material having a second lattice constant, wherein the second lattice constant is different than the first lattice constant to impart a strain on the quantum well channel. Other embodiments may be described and/or claimed.

Abstract translation: 本公开的实施例描述了为诸如水平场效应晶体管等集成电路器件施加应变的技术和配置。 集成电路器件包括半导体衬底，与半导体衬底耦合的第一势垒层，耦合到第一势垒层的量子阱沟道，量子阱沟道包括具有第一晶格常数的第一材料和耦合到 量子阱沟道，源结构包括具有第二晶格常数的第二材料，其中第二晶格常数不同于在量子阱沟道上施加应变的第一晶格常数。 可以描述和/或要求保护其他实施例。

公开(公告)号：US07947971B2

公开(公告)日：2011-05-24

申请号：US12756989

申请日：2010-04-08

Applicant: Prashant Majhi ,  Mantu Hudait ,  Jack T. Kavalieros ,  Ravi Pillarisetty ,  Marko Radosavljevic ,  Gilbert Dewey ,  Titash Rakshit ,  Willman Tsai

Inventor： Prashant Majhi ,  Mantu Hudait ,  Jack T. Kavalieros ,  Ravi Pillarisetty ,  Marko Radosavljevic ,  Gilbert Dewey ,  Titash Rakshit ,  Willman Tsai

IPC: H01L29/06 ,  H01L31/072 ,  H01L31/0336 ,  H01L31/0328 ,  H01L31/109

CPC classification number: H01L29/66431 ,  H01L21/28518 ,  H01L21/76802 ,  H01L21/76805 ,  H01L21/76897 ,  H01L29/152 ,  H01L29/165 ,  H01L29/41766 ,  H01L29/517 ,  H01L29/66462 ,  H01L29/7783 ,  H01L29/7848 ,  H01L29/802

Abstract: Embodiments described include straining transistor quantum well (QW) channel regions with metal source/drains, and conformal regrowth source/drains to impart a uni-axial strain in a MOS channel region. Removed portions of a channel layer may be filled with a junction material having a lattice spacing different than that of the channel material to causes a uni-axial strain in the channel, in addition to a bi-axial strain caused in the channel layer by a top barrier layer and a bottom buffer layer of the quantum well.

Abstract translation: 所描述的实施例包括具有金属源/漏极的应变晶体管量子阱（QW）沟道区，以及保形再生长源/漏极，以在MOS沟道区中赋予单轴应变。 沟道层的去除部分可以填充具有不同于沟道材料的晶格间隔的结合材料，以在通道中引起单轴应变，以及在沟道层中引起的双轴应变 顶部阻挡层和量子阱的底部缓冲层。

公开(公告)号：US07892902B1

公开(公告)日：2011-02-22

申请号：US12653999

申请日：2009-12-22

Applicant: Mantu K. Hudait ,  Marko Radosavljevic ,  Ravi Pillarisetty ,  Gilbert Dewey

Inventor： Mantu K. Hudait ,  Marko Radosavljevic ,  Ravi Pillarisetty ,  Gilbert Dewey

IPC: H01L21/338

CPC classification number: H01L29/205 ,  B82Y10/00 ,  H01L29/122 ,  H01L29/4236 ,  H01L29/66462 ,  H01L29/7783

Abstract: A group III-V material device has multiple spacer regions above a quantum well channel region. A high-k value gate dielectric is formed on an InGaAs spacer above the quantum well channel region while there are InAlAs spacer regions under contact regions.

Abstract translation: III-V族材料器件在量子阱沟道区域上方具有多个间隔区域。 在量子阱沟道区域上方的InGaAs间隔物上形成高k值栅极电介质，而在接触区域处具有InAlAs间隔区域。

公开(公告)号：US07868318B2

公开(公告)日：2011-01-11

申请号：US12291231

申请日：2008-11-07

Applicant: Mantu Hudait ,  Robert S. Chau ,  Marko Radosavljevic ,  Ravi Pillarisetty ,  Gilbert Dewey

Inventor： Mantu Hudait ,  Robert S. Chau ,  Marko Radosavljevic ,  Ravi Pillarisetty ,  Gilbert Dewey

IPC: H01L31/00

CPC classification number: H01L29/7783 ,  H01L29/205 ,  H01L29/517 ,  H01L29/7784

Abstract: A quantum well (QW) layer is provided in a semiconductive device. The QW layer is covered with a composite spacer above QW layer. The composite spacer includes an InP spacer first layer and an InAlAs spacer second layer above and on the InP spacer first layer. The semiconductive device includes InGaAs bottom and top barrier layers respectively below and above the QW layer. The semiconductive device also includes a high-k gate dielectric layer that sits on the InP spacer first layer in a gate recess. A process of forming the QW layer includes using an off-cut semiconductive substrate.

Abstract translation: 在半导体器件中提供量子阱（QW）层。 QW层覆盖有QW层以上的复合间隔物。 复合间隔物包括在InP间隔物第一层上方和之上的InP间隔物第一层和InAlAs间隔物第二层。 半导体器件包括分别在QW层下方和上方的InGaAs底部和顶部势垒层。 半导体器件还包括位于栅极凹槽中的InP间隔物第一层上的高k栅介质层。 形成QW层的方法包括使用切断的半导体衬底。

公开(公告)号：US07858481B2

公开(公告)日：2010-12-28

申请号：US11154138

申请日：2005-06-15

Applicant: Justin K. Brask ,  Robert S. Chau ,  Suman Datta ,  Mark L. Doczy ,  Brian S. Doyle ,  Jack T. Kavalieros ,  Amlan Majumdar ,  Matthew V. Metz ,  Marko Radosavljevic

Inventor： Justin K. Brask ,  Robert S. Chau ,  Suman Datta ,  Mark L. Doczy ,  Brian S. Doyle ,  Jack T. Kavalieros ,  Amlan Majumdar ,  Matthew V. Metz ,  Marko Radosavljevic

IPC: H01L21/336

CPC classification number: H01L29/7848 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/161 ,  H01L29/165 ,  H01L29/24 ,  H01L29/267 ,  H01L29/4236 ,  H01L29/42376 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/66621 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/66818 ,  H01L29/7834 ,  H01L29/7838 ,  H01L29/785 ,  H04B1/3827 ,  Y10S438/926

Abstract: A method of fabricating a MOS transistor having a thinned channel region is described. The channel region is etched following removal of a dummy gate. The source and drain regions have relatively low resistance with the process.

Abstract translation: 描述了制造具有减薄沟道区的MOS晶体管的方法。 在去除虚拟栅极之后蚀刻沟道区。 源极和漏极区域具有相对较低的电阻。

公开(公告)号：US20100117062A1

公开(公告)日：2010-05-13

申请号：US12291231

申请日：2008-11-07

Applicant: Mantu Hudait ,  Robert S. Chau ,  Marko Radosavljevic ,  Ravi Pillarisetty ,  Gilbert Dewey

Inventor： Mantu Hudait ,  Robert S. Chau ,  Marko Radosavljevic ,  Ravi Pillarisetty ,  Gilbert Dewey

IPC: H01L29/12 ,  H01L21/336

CPC classification number: H01L29/7783 ,  H01L29/205 ,  H01L29/517 ,  H01L29/7784

Abstract: A quantum well (QW) layer is provided in a semiconductive device. The QW layer is covered with a composite spacer above QW layer. The composite spacer includes an InP spacer first layer and an InAlAs spacer second layer above and on the InP spacer first layer. The semiconductive device includes InGaAs bottom and top barrier layers respectively below and above the QW layer. The semiconductive device also includes a high-k gate dielectric layer that sits on the InP spacer first layer in a gate recess. A process of forming the QW layer includes using an off-cut semiconductive substrate.

Abstract translation: 在半导体器件中提供量子阱（QW）层。 QW层覆盖有QW层以上的复合间隔物。 复合间隔物包括在InP间隔物第一层上方和之上的InP间隔物第一层和InAlAs间隔物第二层。 半导体器件包括分别在QW层下方和上方的InGaAs底部和顶部势垒层。 半导体器件还包括位于栅极凹槽中的InP间隔物第一层上的高k栅介质层。 形成QW层的方法包括使用切断的半导体衬底。