公开(公告)号：US11713998B2

公开(公告)日：2023-08-01

申请号：US17663915

申请日：2022-05-18

Applicant: STMicroelectronics (Grenoble 2) SAS ,  STMicroelectronics International N.V.

Inventor： Nicolas Moeneclaey ,  Sri Ram Gupta ,  Sarika Kushwaha

IPC: G01J1/42 ,  G01J1/44

CPC classification number: G01J1/4204 ,  G01J1/44 ,  G01J2001/446

Abstract: According to one aspect, an ambient-light sensor includes a photodiode configured to generate an electrical signal according to an ambient light, a capacitive-feedback transimpedance amplifier connected at its input to the photodiode for receiving a signal generated by the photodiode and for generating as an output an amplified signal from the signal generated by the photodiode, and an auto-zero switch at the input of the capacitive-feedback transimpedance amplifier. The ambient-light sensor further includes a control circuit including a bootstrap circuit configured to receive an initial positive- or zero-voltage logic control signal, and then generate, from this initial logic control signal, an adapted logic control signal having a first positive voltage level and a second negative voltage control level for controlling the auto-zero switch.

公开(公告)号：US11710032B2

公开(公告)日：2023-07-25

申请号：US18055245

申请日：2022-11-14

Applicant: STMICROELECTRONICS INTERNATIONAL N.V. ,  STMICROELECTRONICS S.R.L.

Inventor： Surinder Pal Singh ,  Thomas Boesch ,  Giuseppe Desoli

IPC: G06N3/063 ,  G06F17/18 ,  G06N3/04 ,  G06N3/08 ,  G06F18/21

CPC classification number: G06N3/063 ,  G06F17/18 ,  G06F18/217 ,  G06N3/04 ,  G06N3/08

Abstract: A convolutional neural network includes a pooling unit. The pooling unit performs pooling operations between convolution layers of the convolutional neural network. The pooling unit includes hardware blocks that promote computational and area efficiency in the convolutional neural network.

公开(公告)号：US20230231559A1

公开(公告)日：2023-07-20

申请号：US18151337

申请日：2023-01-06

Applicant: STMicroelectronics International N.V.

Inventor： Kallol CHATTERJEE ,  Rohit Kumar GUPTA

IPC: H03K19/0185

CPC classification number: H03K19/018521

Abstract: Provided is a voltage level shifter that operates in sub-threshold voltages. The level shifter includes a level shifting stage. The level shifting stage receives a first signal from a first voltage domain and outputs a second signal to a second voltage domain. The level shifter includes a first auxiliary stage. In response to the first signal having a first voltage level corresponding to a first logical state and a first node of the level shifting stage having a supply voltage level, the first auxiliary stage sources current to a second node of the level shifting stage. Sourcing the current to the second node accelerates a transition of the first node to a reference voltage. The level shifting stage outputs a second signal to a second voltage domain.

公开(公告)号：US11695326B2

公开(公告)日：2023-07-04

申请号：US17058101

申请日：2019-05-14

Applicant: STMicroelectronics International N.V.

Inventor： Laurent Guillot ,  Thierry Sutto ,  Gérald Augustoni

IPC: H02M1/38 ,  H02M3/158

CPC classification number: H02M1/38 ,  H02M3/158

Abstract: A half-bridge electronic device comprises, in series, a low level switch and a high level switch connected at a central point, and respectively controlled by a first and a second activation/deactivation signal. The device comprises: a first and a second synchronization system configured to interpret a variation in the voltage at the central point, respectively along a falling edge and along a rising edge, and to respectively generate a first and a second synchronization signal separate from the first; a first and a second AND type logic gate respectively combining the first synchronization signal with a first control signal and the second synchronization signal with a second control signal, in order to respectively form the first and second activation/deactivation signals.

公开(公告)号：US20230198386A1

公开(公告)日：2023-06-22

申请号：US18168936

申请日：2023-02-14

Applicant: STMicroelectronics International N.V. ,  STMicroelectronics S.r.l.

Inventor： Vikas Rana ,  Marco Pasotti ,  Fabio De Santis

IPC: H02M3/07

CPC classification number: H02M3/07 ,  G11C5/145

Abstract: A voltage supply circuit and a method for controlling a voltage supply circuit are provided. The voltage supply circuit includes a positive charge pump stage that generates a positive voltage and a negative charge pump stage that generates a negative voltage. The voltage supply circuit also includes a control stage that compares a voltage representative of the negative voltage with a reference voltage and causes a slope of the positive voltage to decrease when the voltage representative of the negative voltage exceeds the reference voltage.

公开(公告)号：US20230186067A1

公开(公告)日：2023-06-15

申请号：US18167366

申请日：2023-02-10

Applicant: STMICROELECTRONICS S.r.l. ,  STMICROELECTRONICS INTERNATIONAL N.V.

Inventor： Surinder Pal SINGH ,  Thomas BOESCH ,  Giuseppe DESOLI

IPC: G06N3/063 ,  G06T7/62 ,  G06T7/11 ,  G06F16/901 ,  G06F9/38 ,  G06N3/08 ,  G06T15/08 ,  G06V10/82 ,  G06F18/22 ,  G06N3/045

CPC classification number: G06N3/063 ,  G06T7/62 ,  G06T7/11 ,  G06F16/9024 ,  G06F9/3877 ,  G06N3/08 ,  G06T15/08 ,  G06V10/82 ,  G06F18/22 ,  G06N3/045

Abstract: A device include on-board memory, an applications processor, a digital signal processor (DSP) cluster, a configurable accelerator framework (CAF), and a communication bus architecture. The communication bus communicatively couples the applications processor, the DSP cluster, and the CAF to the on-board memory. The CAF includes a reconfigurable stream switch and data volume sculpting circuitry, which has an input and an output coupled to the reconfigurable stream switch. The data volume sculpting circuitry receives a series of frames, each frame formed as a two dimensional (2D) data structure, and determines a first dimension and a second dimension of each frame of the series of frames. Based on the first and second dimensions, the data volume sculpting circuitry determines for each frame a position and a size of a region-of-interest to be extracted from the respective frame, and extracts from each frame, data in the frame that is within the region-of-interest.

公开(公告)号：US11658624B2

公开(公告)日：2023-05-23

申请号：US17461123

申请日：2021-08-30

Applicant: STMicroelectronics International N.V.

Inventor： Riju Biswas ,  Ratul Mitra

IPC: H03F3/45

CPC classification number: H03F3/45085 ,  H03F3/45475 ,  H03F2203/45006 ,  H03F2203/45026 ,  H03F2203/45048 ,  H03F2203/45084 ,  H03F2203/45088 ,  H03F2203/45211

Abstract: Disclosed herein is a method including sinking current from a pair of input transistors of a differential amplifier while sourcing more current to the pair of input transistors than is sunk. The method further includes generating a pair of input differential signals using a pair of input voltage regulators, and amplifying a difference between the pair of input differential signals to produce a pair of differential output voltages, using the differential amplifier. The method also includes amplifying the pair of differential output voltages using at least one voltage gain amplifier, and generating control signals for current sources that source the current to the pair of input transistors of the differential amplifier, from the pair of differential output voltages after at least amplification.

公开(公告)号：US20230140251A1

公开(公告)日：2023-05-04

申请号：US17965282

申请日：2022-10-13

Applicant: STMicroelectronics International N.V.

Inventor： Atul DWIVEDI

IPC: G01K7/01 ,  H03M1/36 ,  H03M1/12 ,  H03M1/46 ,  G01K7/18

Abstract: A temperature sensing circuit includes a current generation circuit generating an initial current proportional to absolute temperature (Iptat), and a voltage generation circuit configured to mirror Iptat using an adjustable current source to produce a scaled current and to source the scaled current to a first terminal of a resistor to produce a reference voltage at the first terminal. A second terminal of the resistor has a voltage complementary to absolute temperature (Vctat) applied thereto. An analog-to-digital converter (ADC) has a reference input receiving the reference voltage, and a data input receiving Vctat or an externally sourced voltage. The ADC generates an output code indicative of a ratio between: a) either Vctat or the externally sourced voltage, and b) the reference voltage. A digital circuit determines a temperature readout from the output code and calibrates the reference voltage and the temperature readout determination based upon the output code.

公开(公告)号：US20230135185A1

公开(公告)日：2023-05-04

申请号：US18055245

申请日：2022-11-14

Applicant: STMICROELECTRONICS INTERNATIONAL N.V. ,  STMICROELECTRONICS S.R.L.

Inventor： Surinder Pal SINGH ,  Thomas BOESCH ,  Giuseppe DESOLI

IPC: G06N3/063 ,  G06F17/18 ,  G06N3/04 ,  G06N3/08 ,  G06F18/21

Abstract: A convolutional neural network includes a pooling unit. The pooling unit performs pooling operations between convolution layers of the convolutional neural network. The pooling unit includes hardware blocks that promote computational and area efficiency in the convolutional neural network.

公开(公告)号：US20230133385A1

公开(公告)日：2023-05-04

申请号：US17515149

申请日：2021-10-29

Applicant: STMicroelectronics Application GmbH ,  STMicroelectronics International N.V.

Inventor： Avneep Kumar Goyal ,  Thomas Szurmant

IPC: G06F21/44 ,  G06F21/31 ,  G06F21/85 ,  G06F11/36

Abstract: A system on a chip including a first-port controller for a first development port configured to receive a first development tool and a second-port controller for a second development port configured to receive a second development tool. The system on a chip further including a central controller in communication with the first-port controller, the second-port controller, and a security subsystem. The central controller being configured to manage authentication exchanges between the security subsystem and the first development tool and authentication exchanges between the security subsystem and the second development tool.