公开(公告)号：US08922254B2

公开(公告)日：2014-12-30

申请号：US13913139

申请日：2013-06-07

Applicant: Macronix International Co., Ltd.

Inventor： Shang-Chi Yang ,  Ken-Hui Chen ,  Su-Chueh Lo ,  Kuen-Long Chang ,  Chun-Hsiung Hung

IPC: H03B1/00 ,  H03K3/00 ,  H03K17/14

CPC classification number: H03K17/145

Abstract: Current drivers and biasing circuitry at least partly compensate for manufacturing variations and environmental variations such as supply voltage, temperature, and fabrication process.

Abstract translation: 电流驱动器和偏置电路至少部分地补偿制造变化和环境变化，例如电源电压，温度和制造过程。

公开(公告)号：US08738849B2

公开(公告)日：2014-05-27

申请号：US13686917

申请日：2012-11-28

Applicant: Macronix International Co., Ltd.

Inventor： Chun-Hsiung Hung ,  Kuen-Long Chang ,  Chia-He Liu

IPC: G06F12/00

CPC classification number: G06F3/0659 ,  G06F3/0604 ,  G06F3/0673 ,  G06F12/00 ,  G06F13/4286

Abstract: A method of conducting an operation in an integrated circuit having a plurality of memory cells includes receiving an operating command for the memory cells and receiving a first address segment associated with the memory cells in at least one clock cycle after receiving the operating command. The method further includes receiving a first performance enhancement indicator in at least one clock cycle after ending the first address segment while before starting to transfer data, for determining whether an enhanced operation is to be performed.

Abstract translation: 在具有多个存储单元的集成电路中执行操作的方法包括在接收到操作命令之后的至少一个时钟周期中接收用于存储器单元的操作命令并接收与存储器单元相关联的第一地址段。 该方法还包括在开始传送数据之前，在结束第一地址段之后的至少一个时钟周期内接收第一性能增强指示符，以确定是否执行增强的操作。

公开(公告)号：US20130086294A1

公开(公告)日：2013-04-04

申请号：US13687586

申请日：2012-11-28

Applicant: Macronix International Co., Ltd.

Inventor： Yu-Lan Kuo ,  Chun-Hsiung Hung

IPC: G06F13/40

CPC classification number: G06F13/4291 ,  G06F1/22 ,  G06F13/385 ,  G06F13/40 ,  G06F13/4022 ,  G06F13/404

Abstract: A serial peripheral interface of an integrated circuit including multiple pins and a clock pin is provided. The pins are coupled to the integrated circuit for transmitting an instruction, an address or a read out data. The clock pin is coupled to the integrated circuit for inputting multiple timing pulses. The plurality of pins transmit the instruction, the address or the read out data at rising edges, falling edges or both edges of the timing pulses.

Abstract translation: 提供了包括多个引脚和时钟引脚的集成电路的串行外设接口。 引脚耦合到集成电路，用于发送指令，地址或读出数据。 时钟引脚耦合到集成电路，用于输入多个定时脉冲。 多个引脚在定时脉冲的上升沿，下降沿或两个边缘发送指令，地址或读出数据。