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    Methods and apparatuses for executing a plurality of queued tasks in a memory
    163.
    发明授权
    Methods and apparatuses for executing a plurality of queued tasks in a memory 有权

    公开(公告)号：US11023167B2

    公开(公告)日：2021-06-01

    申请号：US16136101

    申请日：2018-09-19

    Applicant: Micron Technology, Inc.

    Inventor： Giuseppe D'Eliseo ,  Graziano Mirichigni ,  Danilo Caraccio ,  Luca Porzio ,  Antonino Pollio

    IPC: G06F12/00 ,  G06F3/06

    Abstract: Methods and apparatuses are disclosed for executing a plurality of queued tasks in a memory. One example apparatus includes a memory configured to be coupled to a host. The memory is also configured to receive a plurality of memory access requests, a status request, and an execution command from the host, and to execute one or more of the plurality of memory access requests responsive to the execution command from the host. The execution command includes a plurality of respective indications that correspond to each respective memory access request of the plurality of memory access requests and that indicate whether the host is requesting the memory to execute each respective memory access request.

    Data state synchronization
    164.
    发明授权
    Data state synchronization 有权

    公开(公告)号：US10943659B2

    公开(公告)日：2021-03-09

    申请号：US16744643

    申请日：2020-01-16

    Applicant: Micron Technology, Inc.

    Inventor： Marco Dallabora ,  Paolo Amato ,  Daniele Balluchi ,  Danilo Caraccio ,  Emanuele Confalonieri

    IPC: G11C11/00 ,  G11C13/00 ,  G06F13/16

    Abstract: The present disclosure includes apparatuses, and methods for data state synchronization. An example apparatus includes performing a write operation to store a data pattern in a group of resistance variable memory cells corresponding to a selected managed unit having a first status, updating a status of the selected managed unit from the first status to a second status responsive to performing the write operation, and providing data state synchronization for a subsequent write operation performed on the group by placing all of the variable resistance memory cells of the group in a same state prior to performing the subsequent write operation to store another data pattern in the group of resistance variable memory cells.

    Storage class memory status
    165.
    发明授权
    Storage class memory status 有权

    公开(公告)号：US10891223B2

    公开(公告)日：2021-01-12

    申请号：US16824314

    申请日：2020-03-19

    Applicant: Micron Technology, Inc.

    Inventor： Luca Porzio ,  Graziano Mirichigni ,  Danilo Caraccio

    IPC: G06F12/00 ,  G06F12/02 ,  G06F12/1009 ,  G06F3/06 ,  G11C29/52

    Abstract: Devices and techniques for storage class memory status are disclosed herein. A storage portion characteristics data structure is maintained. Here, the data structure includes an array of elements—where each element is sized to contain a reference to a storage portion in a storage class memory storage device, a first pointer to a first element in the array of elements, a second pointer to a second element in the array of elements, and a third pointer to a third element in the array of elements. The data structure includes a direction of pointer motion in which the second pointer precedes the third pointer and the first pointer precedes the second pointer with respect to the direction of pointer motion. A write request is performed to a storage portion reference retrieved from the first element. The first pointer is then advanced.

    Command queuing
    166.
    发明授权
    Command queuing 有权

    公开(公告)号：US10884661B2

    公开(公告)日：2021-01-05

    申请号：US16207453

    申请日：2018-12-03

    Applicant: Micron Technology, Inc.

    Inventor： Victor Y. Tsai ,  Danilo Caraccio ,  Daniele Balluchi ,  Neal A. Galbo ,  Robert Warren

    IPC: G06F3/06

    Abstract: The present disclosure includes apparatuses and methods for command queuing. A number of embodiments include receiving a queued command request at a memory system from a host, sending a command response from the memory system to the host that indicates the memory system is ready to receive a command in a command queue of the memory system, and receiving, in response to sending the command response, a command descriptor block for the command at the memory system from the host.

    STORAGE CLASS MEMORY STATUS
    167.
    发明申请
    STORAGE CLASS MEMORY STATUS 审中-公开

    公开(公告)号：US20200218645A1

    公开(公告)日：2020-07-09

    申请号：US16824314

    申请日：2020-03-19

    Applicant: Micron Technology, Inc.

    Inventor： Luca Porzio ,  Graziano Mirichigni ,  Danilo Caraccio

    IPC: G06F12/02 ,  G06F3/06 ,  G11C29/52 ,  G06F12/1009

    Abstract: Devices and techniques for storage class memory status are disclosed herein. A storage portion characteristics data structure is maintained. Here, the data structure includes an array of elements—where each element is sized to contain a reference to a storage portion in a storage class memory storage device, a first pointer to a first element in the array of elements, a second pointer to a second element in the array of elements, and a third pointer to a third element in the array of elements. The data structure includes a direction of pointer motion in which the second pointer precedes the third pointer and the first pointer precedes the second pointer with respect to the direction of pointer motion. A write request is performed to a storage portion reference retrieved from the first element. The first pointer is then advanced.

    DATA STATE SYNCHRONIZATION
    169.
    发明申请
    DATA STATE SYNCHRONIZATION 审中-公开

    公开(公告)号：US20200082900A1

    公开(公告)日：2020-03-12

    申请号：US16128113

    申请日：2018-09-11

    Applicant: Micron Technology, Inc.

    Inventor： Paolo Amato ,  Marco Dallabora ,  Daniele Balluchi ,  Danilo Caraccio ,  Emanuele Confalonieri

    IPC: G11C29/42 ,  G11C29/44 ,  G11C13/00 ,  G11C7/22 ,  G06F11/10

    Abstract: An example apparatus includes a memory comprising a plurality of managed units corresponding to respective groups of resistance variable memory cells and a controller coupled to the memory. The controller is configured to cause performance of a cleaning operation on a selected group of the memory cells and generation of error correction code (ECC) parity data. The controller may be further configured to cause performance of a write operation on the selected group of cells to write an inverted state of at least one data value to the selected group of cells and write an inverted state of at least one of the ECC parity data to the selected group of cells.

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