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公开(公告)号：US12266569B2
公开(公告)日：2025-04-01
申请号：US18416243
申请日：2024-01-18
Applicant: Micron Technology, Inc.
Inventor： John D. Hopkins , Shuangqiang Luo , Alyssa N. Scarbrough
IPC: H01L23/535 , H01L21/768 , H10B41/27 , H10B43/27
Abstract: Integrated circuitry comprises vertical conductive vias individually having a lower portion thereof that is directly against conductor material of islands. The islands comprise multiple different composition materials directly above the conductor material. Apart from the conductive vias, the islands individually comprise at least one of (a), (b), or (c), where: (a): a top material that is of different composition from all material that is vertically between the top material and the conductor material; (b): the top material having its top surface in a vertical cross-section extending laterally-outward beyond two opposing laterally-outermost edges of a top surface of the material that is immediately directly below the top material; and (c): is of different composition from that of an upper portion of the conductor material and including a portion thereof that is elevationally coincident with the conductor material or that is directly against the conductor material. Other embodiments, including methods, are disclosed.
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公开(公告)号：US12219757B2
公开(公告)日：2025-02-04
申请号：US17836357
申请日：2022-06-09
Applicant: Micron Technology, Inc.
Inventor： John D. Hopkins , Nancy M. Lomeli
Abstract: A memory array comprising strings of memory cells comprises laterally-spaced memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers. Channel-material-string structures of memory cells extend through the insulative tiers and the conductive tiers. The channel-material-string structures individually comprise an upper portion above and joined with a lower portion. Individual of the channel-material-string structures comprise at least one external jog surface in a vertical cross-section where the upper and lower portions join. Other embodiments, including method are disclosed.
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公开(公告)号：US12198762B2
公开(公告)日：2025-01-14
申请号：US17409355
申请日：2021-08-23
Applicant: Micron Technology, Inc.
Inventor： Alyssa N. Scarbrough , John D. Hopkins , Jordan D. Greenlee
Abstract: A memory array comprising strings of memory cells comprises laterally-spaced memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers above a conductor tier. Strings of memory cells comprise channel-material strings that extend through the insulative tiers and the conductive tiers. The channel-material strings directly electrically couple to conductor material of the conductor tier. The insulative tier immediately-above a lowest of the conductive tiers comprises a lower first insulating material and an upper second insulating material above the upper first insulating material. The upper second insulating material is of different composition from that of the lower first insulating material. Intervening material is laterally-between and longitudinally-along immediately-laterally-adjacent of the memory blocks. Other embodiments, including method, are disclosed.
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公开(公告)号：US12176035B2
公开(公告)日：2024-12-24
申请号：US17583651
申请日：2022-01-25
Applicant: Micron Technology, Inc.
Inventor： Alyssa N. Scarbrough , John D. Hopkins
IPC: H01L29/76 , G11C16/04 , H01L23/522 , H01L23/528 , H10B41/10 , H10B41/27 , H10B43/10 , H10B43/27
Abstract: A memory array comprising strings of memory cells comprises laterally-spaced memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers directly above a conductor tier. Strings of memory cells comprise channel-material strings that extend through the insulative tiers and the conductive tiers. The channel-material strings directly electrically couple with conductor material of the conductor tier. A through-array-via (TAV) region comprises TAVs that individually extend through the insulative tiers and the conductive tiers into the conductor tier. Individual of the TAVs comprises an upper portion directly above and joined with a lower portion. The individual TAVs in a vertical cross-section comprises at least one external upper jog surface. The individual TAVs comprise at least one external lower jog surface in the conductor tier in the vertical cross-section and that is below the upper jog surface. Other embodiments, including method, are disclosed.
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公开(公告)号：US12159674B2
公开(公告)日：2024-12-03
申请号：US17409476
申请日：2021-08-23
Applicant: Micron Technology, Inc.
Inventor： Jordan D. Greenlee , John D. Hopkins , M. Jared Barclay , Andrew Li , Aireus Christensen
Abstract: A method used in forming a memory array comprising strings of memory cells comprises forming a conductor tier comprising conductor material on a substrate. Laterally-spaced memory-block regions are formed that individually comprise a vertical stack comprising alternating first tiers and second tiers are formed directly above the conductor tier. Material of the first tiers is sacrificial and of different composition from material of the first tiers. Channel-material strings extend through the first tiers and the second tiers. Conducting material in a lowest of the first tiers is formed that directly electrically couples together the channel material of individual of the channel-material strings and the conductor material of the conductor tier. A horizontally-elongated trench is formed between immediately-laterally-adjacent of the memory-block regions. The trenches extend downwardly into the conducting material. After forming the trenches, lateral-sidewall regions of the conducting material that are aside the individual trenches in the lowest first tier is doped with an impurity. The sacrificial material is etched from the first tiers through the trenches selectively relative to the doped lateral-sidewall regions of the conducting material. Other embodiments, including structure, are disclosed.
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Patent Agency Ranking
166.发明公开公开(公告)号：US20240339357A1
公开(公告)日：2024-10-10
申请号：US18745872
申请日：2024-06-17
Applicant: Micron Technology, Inc.
Inventor： Darwin A. Clampitt , John D. Hopkins , Madison D. Drake
IPC: H01L21/768 , H01L23/532 , H01L23/535 , H10B41/27 , H10B43/27
CPC classification number: H01L21/7682 , H01L21/76805 , H01L21/76895 , H01L23/53257 , H01L23/5329 , H01L23/535 , H10B41/27 , H10B43/27
Abstract: A microelectronic device comprises a stack structure comprising a vertically alternating sequence of conductive structures and insulative structures arranged in tiers, strings of memory cells vertically extending through the stack structure, the strings of memory cells individually comprising a channel material vertically extending through the stack structure, a conductive contact structure vertically overlying and in electrical communication with the channel material of a string of memory cells of the strings of memory cells, and a void laterally neighboring the conductive contact structure, the conductive contact structure separated from a laterally neighboring conductive contact structure by the void, a dielectric material, and an additional void laterally neighboring the laterally neighboring conductive contact structure. Related memory devices, electronic systems, and methods are also described.
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167.发明公开公开(公告)号：US20240274198A1
公开(公告)日：2024-08-15
申请号：US18643554
申请日：2024-04-23
Applicant: Micron Technology, Inc.
Inventor： Jordan D. Greenlee , John D. Hopkins , Andrew Li , Alyssa N. Scarbrough
CPC classification number: G11C16/0483 , H01L29/161 , H10B41/10 , H10B41/27 , H10B41/35 , H10B43/10 , H10B43/27 , H10B43/35
Abstract: A memory array comprising laterally-spaced memory blocks individually comprises a vertical stack comprising alternating insulative tiers and conductive tiers. Channel-material strings of memory cells extend through the insulative tiers and the conductive tiers. The laterally-spaced memory blocks in a lower one of the conductive tiers comprises elemental-form metal that extends longitudinally-along the laterally-spaced memory blocks proximate laterally -outer sides of the laterally-spaced memory blocks. A metal silicide or a metal-germanium compound is directly against laterally-inner sides of the elemental-form metal in the lower conductive tier and that extends longitudinally-along the laterally-spaced memory blocks in the lower conductive tier. The metal of the metal silicide or of the metal-germanium compound is the same as that of the elemental-form metal. Other embodiments, including method, are disclosed.
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公开(公告)号：US20240251554A1
公开(公告)日：2024-07-25
申请号：US18584275
申请日：2024-02-22
Applicant: Micron Technology, Inc.
Inventor： Alyssa N. Scarbrough , Jordan D. Greenlee , John D. Hopkins
Abstract: Some embodiments include an integrated assembly having a memory region and another region adjacent the memory region. Channel-material-pillars are arranged within the memory region, and conductive posts are arranged within said other region. A source structure is coupled to lower regions of the channel-material-pillars. A panel extends across the memory region and the other region. Doped-semiconductor-material is directly adjacent to the panel within the memory region and the other region. The doped-semiconductor-material is at least part of the source structure within the memory region. Liners are directly adjacent to the conductive posts and laterally surround the conductive posts. The liners are between the conductive posts and the doped-semiconductor-material. Some embodiments include methods of forming integrated assemblies.
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公开(公告)号：US12041769B2
公开(公告)日：2024-07-16
申请号：US18047245
申请日：2022-10-17
Applicant: Micron Technology, Inc.
Inventor： John D. Hopkins , Jordan D. Greenlee , Nancy M. Lomeli
Abstract: A method of forming a microelectronic device comprises forming a sacrificial material over a base structure. Portions of the sacrificial material are replaced with an etch-resistant material. A stack structure is formed over the etch-resistant material and remaining portions of the sacrificial material. The stack structure comprises a vertically alternating sequence of insulative material and additional sacrificial material arranged in tiers, and at least one staircase structure horizontally overlapping the etch-resistant material and having steps comprising horizontal ends of the tiers. Slots are formed to vertically extend through the stack structure and the remaining portions of the sacrificial material. The sacrificial material and the additional sacrificial material are selectively replaced with conductive material after forming the slots to respectively form lateral contact structures and conductive structures. Microelectronic devices, memory devices, and electronic systems are also described.
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170.发明公开公开(公告)号：US20240237352A1
公开(公告)日：2024-07-11
申请号：US18581667
申请日：2024-02-20
Applicant: Micron Technology, Inc.
Inventor： Darwin A. Clampitt , John D. Hopkins , Matthew J. King , Roger W. Lindsay , Kevin Y. Titus
IPC: H10B43/27 , H01L23/522 , H10B41/27
CPC classification number: H10B43/27 , H01L23/5226 , H10B41/27
Abstract: A microelectronic device includes a pair of stack structures. The pair comprises a lower stack structure and an upper stack structure overlying the lower stack structure. The lower stack structure and the upper stack structure each comprise a vertically alternating sequence of insulative structures and conductive structures arranged in tiers. A source region is vertically interposed between the lower stack structure and the upper stack structure. A first array of pillars extends through the upper stack structure, from proximate the source region toward a first drain region above the upper stack structure. A second array of pillars extend through the lower stack structure, from proximate the source region toward a second drain region below the lower stack structure. Additional microelectronic devices are also disclosed, as are related methods and electronic systems.
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