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    System And Method For Storing Multibit Data In Non-volatile Memory
    161.
    发明申请
    System And Method For Storing Multibit Data In Non-volatile Memory 审中-公开

    公开(公告)号：US20190139602A1

    公开(公告)日：2019-05-09

    申请号：US16148304

    申请日：2018-10-01

    Applicant: Silicon Storage Technology, Inc.

    Inventor： Vipin Tiwari ,  Nhan Do ,  Hieu Van Tran

    IPC: G11C11/56 ,  G11C16/04 ,  G11C16/26 ,  G11C16/34

    Abstract: A method of reading a memory device having a plurality of memory cells by, and a device configured for, reading a first memory cell of the plurality of memory cells to generate a first read current, reading a second memory cell of the plurality of memory cells to generate a second read current, applying a first offset value to the second read current, and then combining the first and second read currents to form a third read current, and then determining a program state using the third read current. Alternately, a first voltage is generated from the first read current, a second voltage is generated from the second read current, whereby the offset value is applied to the second voltage, wherein the first and second voltages are combined to form a third voltage, and then the program state is determined using the third voltage.

    Method of forming split gate memory cells with 5 volt logic devices
    165.
    发明授权
    Method of forming split gate memory cells with 5 volt logic devices 有权
    用5伏逻辑器件形成分离栅极存储单元的方法

    公开(公告)号：US09570592B2

    公开(公告)日：2017-02-14

    申请号：US15164796

    申请日：2016-05-25

    Applicant: Silicon Storage Technology, Inc.

    Inventor： Nhan Do ,  Vipin Tiwari

    IPC: H01L21/28 ,  H01L21/265 ,  H01L21/768 ,  H01L29/66 ,  H01L27/115

    CPC classification number: H01L29/66825 ,  H01L21/28273 ,  H01L27/11529 ,  H01L29/66484 ,  H01L29/7885

    Abstract: A method of forming a memory device on a semiconductor substrate having a memory region (with floating and control gates), a first logic region (with first logic gates) and a second logic region (with second logic gates). A first implantation forms the source regions adjacent the floating gates in the memory region, and the source and drain regions adjacent the first logic gates in the first logic region. A second implantation forms the source and drain regions adjacent the second logic gates in the second logic region. A third implantation forms the drain regions adjacent the control gates in the memory region, and enhances the source region in the memory region and the source/drain regions in the first logic region. A fourth implantation enhances the source/drain regions in the second logic region.

    Abstract translation: 在具有存储区域（具有浮动和控制栅极）的第一逻辑区域（具有第一逻辑门）和第二逻辑区域（具有第二逻辑门）的半导体衬底上形成存储器件的方法。 第一注入形成与存储区域中的浮置栅极相邻的源极区域，以及与第一逻辑区域中的第一逻辑门极相邻的源区域和漏极区域。 第二注入形成与第二逻辑区域中的第二逻辑门相邻的源区和漏区。 第三注入形成与存储器区域中的控制栅极相邻的漏极区域，并且增强第一逻辑区域中的存储区域和源极/漏极区域中的源极区域。 第四次注入增强了第二逻辑区域中的源极/漏极区域。

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