公开(公告)号：US11756952B2

公开(公告)日：2023-09-12

申请号：US18066154

申请日：2022-12-14

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Kuang-Ching Chang ,  Jung-Chan Yang ,  Hui-Zhong Zhuang ,  Chih-Liang Chen ,  Kuo-Nan Yang

IPC: H01L27/02 ,  G06F1/3287

CPC classification number: H01L27/0207 ,  G06F1/3287

Abstract: An integrated circuit includes a gated circuit configured to operate on a first or second voltage, a header circuit, a first power rail and a second power rail on a back-side of a wafer, a third power rail on the back-side of the wafer, and a fourth power rail on a front-side of the wafer. The first and second power rail extend in a first direction, and are separated from each other in a second direction. The third power rail is between the first and second power rail in the second direction. The third power rail is configured to supply the second voltage to the gated circuit. The fourth power rail includes a first set of conductors extending in the second direction. Each of the first set of conductors is configured to supply a third voltage to the header circuit, and is separated from each other in the first direction.

公开(公告)号：US20230281373A1

公开(公告)日：2023-09-07

申请号：US17856412

申请日：2022-07-01

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Shang-Hsuan Chiu ,  Chih-Liang Chen ,  Hui-Zhong Zhuang ,  Chi-Yu Lu ,  Jerry Chang Jui Kao

IPC: G06F30/392

CPC classification number: G06F30/392 ,  G06F2119/18

Abstract: Metallization structure for an integrated circuit. In one embodiment, an integrated circuit includes a metal-to-diffusion (MD) layer disposed over an active region of a cell, gates disposed over the active region of the cell, and a first metallization layer including M0 tracks disposed over the MD layer and the gates. The integrated circuit further includes a second metallization layer including M1 tracks disposed over the first metallization layer. The M1 tracks include first M1 tracks each having a first predetermined distance from an edge of the cell and second M1 tracks each having a second predetermined distance from the edge of the cell, wherein the first MI tracks are longer than the second M1 tracks.

公开(公告)号：US11735625B2

公开(公告)日：2023-08-22

申请号：US17037438

申请日：2020-09-29

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： Jung-Chan Yang ,  Hui-Zhong Zhuang ,  Chih-Liang Chen ,  Ting-Wei Chiang ,  Cheng-I Huang ,  Kuo-Nan Yang

IPC: H01L29/06 ,  H01L27/092

CPC classification number: H01L29/0653 ,  H01L27/092

Abstract: A semiconductor device, including: a first OD strip, a first doping region, a second OD strip, a second doping region, and a third doping region. The first OD strip extending in a first direction is disposed on the first OD strip, and includes a first-type dopant to define an active region of a first MOS. The second OD strip extending in the first direction and immediately adjacent to the first OD strip in a second direction, wherein the second direction is orthogonal with the first direction. The second doping region is disposed on the second OD strip, and includes a second-type dopant to define an active region of a second MOS. The third doping region is disposed on the second OD strip, and includes the second-type dopant and is configured to be a body terminal of the first MOS.

公开(公告)号：US11715733B2

公开(公告)日：2023-08-01

申请号：US17313474

申请日：2021-05-06

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Wei-Ren Chen ,  Cheng-Yu Lin ,  Hui-Zhong Zhuang ,  Yung-Chen Chien ,  Jerry Chang Jui Kao ,  Huang-Yu Chen ,  Chung-Hsing Wang

IPC: H01L27/02 ,  H01L27/092 ,  G06F30/394 ,  H01L21/8238 ,  G06F30/392 ,  H01L23/522

CPC classification number: H01L27/0207 ,  G06F30/392 ,  G06F30/394 ,  H01L21/823871 ,  H01L23/5226 ,  H01L27/092

Abstract: An integrated circuit (IC) device includes a substrate, and a cell over the substrate. The cell includes at least one active region and at least one gate region extending across the at least one active region. The cell further includes at least one input/output (IO) pattern configured to electrically couple one or more of the at least one active region and the at least one gate region to external circuitry outside the cell. The at least one IO pattern extends obliquely to both the at least one active region and the at least one gate region.

公开(公告)号：US11664383B2

公开(公告)日：2023-05-30

申请号：US17330246

申请日：2021-05-25

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： Hsueh-Chih Chou ,  Chia Hao Tu ,  Sang Hoo Dhong ,  Lee-Chung Lu ,  Li-Chun Tien ,  Ting-Wei Chiang ,  Hui-Zhong Zhuang

IPC: H01L27/118 ,  H01L27/02

CPC classification number: H01L27/11807 ,  H01L27/0207 ,  H01L2027/11812 ,  H01L2027/11814 ,  H01L2027/11816 ,  H01L2027/11822 ,  H01L2027/11848 ,  H01L2027/11866 ,  H01L2027/11872 ,  H01L2027/11874 ,  H01L2027/11875

Abstract: A semiconductor structure is disclosed. The semiconductor structure includes: a first standard cell; and a second standard cell; wherein a cell width of the first standard cell along a first direction is substantially the same as a cell width of the second standard cell along the first direction, and a cell height of the first standard cell along a second direction perpendicular to the first direction is substantially greater than a cell height of the second standard cell along the second direction.

公开(公告)号：US11652102B2

公开(公告)日：2023-05-16

申请号：US17132447

申请日：2020-12-23

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Kam-Tou Sio ,  Chih-Liang Chen ,  Charles Chew-Yuen Young ,  Hui-Zhong Zhuang ,  Jiann-Tyng Tzeng ,  Yi-Hsun Chiu

IPC: H01L27/085 ,  H01L27/02 ,  H01L27/092 ,  H01L27/118 ,  H01L21/8238

CPC classification number: H01L27/085 ,  H01L27/0207 ,  H01L27/092 ,  H01L27/118 ,  H01L27/11807 ,  H01L21/823871 ,  H01L21/823892 ,  H01L2027/1189

Abstract: An integrated circuit structure includes a first well, a second well, a third well, a first set of implants and a second set of implants. The first well includes a first dopant type, a first portion extending in a first direction and having a first width, and a second portion adjacent to the first portion of the first well, extending in the first direction and having a second width. The second well has a second dopant type and is adjacent to the first well. The third well has the second dopant type, and is adjacent to the first well. The first portion of the first well is between the second well and the third well. The first set of implants is in the first portion of the first well, the second well and the third well. The second set of implants is in the second portion of the first well.

公开(公告)号：US11632102B2

公开(公告)日：2023-04-18

申请号：US17338199

申请日：2021-06-03

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Yung-Chen Chien ,  Xiangdong Chen ,  Hui-Zhong Zhuang ,  Tzu-Ying Lin ,  Jerry Chang Jui Kao ,  Lee-Chung Lu

IPC: H03K3/3562 ,  H03K3/037 ,  H03K3/012

Abstract: A semiconductor device and a method of operating a semiconductor device are provided. The semiconductor device includes a first latching circuit and a second latching circuit coupled to the first latching circuit. The second latching circuit includes a first feedback circuit and a first transmission circuit, the first feedback circuit configured to receive a first clock signal of a first phase and a second clock signal of a second phase, and the first transmission circuit configured to receive the second clock signal and a third clock signal of a third phase. The first feedback circuit is configured to be turned off by the first clock signal and the second clock signal before the first transmission circuit is turned on by the second clock signal and the third clock signal.

公开(公告)号：US11574110B2

公开(公告)日：2023-02-07

申请号：US16206960

申请日：2018-11-30

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Jung-Chan Yang ,  Ting-Wei Chiang ,  Jerry Chang-Jui Kao ,  Hui-Zhong Zhuang ,  Lee-Chung Lu ,  Li-Chun Tien ,  Meng-Hung Shen ,  Shang-Chih Hsieh ,  Chi-Yu Lu

IPC: G06F30/394 ,  H01L27/118 ,  H01L23/522 ,  H01L23/528 ,  H01L27/02

Abstract: A method of fabricating an integrated circuit structure includes placing a first set of conductive structure layout patterns on a first layout level, placing a second set of conductive structure layout patterns on a second layout level, placing a first set of via layout patterns between the second set of conductive structure layout patterns and the first set of conductive structure layout patterns, and manufacturing the integrated circuit structure based on at least one of the layout patterns of the integrated circuit. At least one of the layout patterns is stored on a non-transitory computer-readable medium, and at least one of the placing operations is performed by a hardware processor. The first set of conductive structure layout patterns extends in a first direction. The second set of conductive structure layout patterns extends in the second direction, and overlap the first set of conductive structure layout patterns.

公开(公告)号：US11556688B2

公开(公告)日：2023-01-17

申请号：US17209918

申请日：2021-03-23

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Jian-Sing Li ,  Hui-Zhong Zhuang ,  Jung-Chan Yang ,  Ting Yu Chen ,  Ting-Wei Chiang ,  Tzu-Ying Lin ,  Li-Chun Tien

IPC: G06F30/392 ,  H01L27/02

Abstract: A method includes positioning a first active region adjacent to a pair of second active regions in an initial integrated circuit (IC) layout diagram of an initial cell, to align side edges of the first active region and corresponding side edges of each second active region of the pair of second active regions along a cell height direction. The first active region forms, together with the initial cell, a modified cell having a modified IC layout diagram. The side edges of the first active region and the corresponding side edges of each second active region extend along the cell height direction. A height dimension of the first active region in the cell height direction is less than half of a height dimension of each second active region of the pair of second active regions in the cell height direction. The positioning the first active region is executed by a processor.

公开(公告)号：USRE49331E1

公开(公告)日：2022-12-13

申请号：US15956629

申请日：2018-04-18

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Lee-Chung Lu ,  Li-Chun Tien ,  Hui-Zhong Zhuang ,  Chang-Yu Wu

IPC: H01L27/02 ,  H01L27/092 ,  G06F30/392

Abstract: A set of masks corresponds to an integrated circuit layout. The integrated circuit layout includes a first cell having a first transistor region and a second transistor region, and a second cell having a third transistor region and a fourth transistor region. The first cell and the second cell adjoin each other at side cell boundaries thereof, the first transistor region and the third transistor region are formed in a first continuous active region, and the second transistor region and the fourth transistor region are formed in a second continuous active region. The set of masks is formed based on the integrated circuit layout.