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    Method and device for forming metal gate electrodes for transistors
    163.
    发明授权
    Method and device for forming metal gate electrodes for transistors 有权

    公开(公告)号：US12205819B2

    公开(公告)日：2025-01-21

    申请号：US18061794

    申请日：2022-12-05

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Huan-Chieh Su ,  Zhi-Chang Lin ,  Ting-Hung Hsu ,  Jia-Ni Yu ,  Wei-Hao Wu ,  Yu-Ming Lin ,  Chih-Hao Wang

    IPC: H01L29/66 ,  H01L21/28 ,  H01L21/308 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/51 ,  H01L29/78

    Abstract: A semiconductor device includes a first transistor and a second transistor. The first transistor includes: a first source and a first drain separated by a first distance, a first semiconductor structure disposed between the first source and first drain, a first gate electrode disposed over the first semiconductor structure, and a first dielectric structure disposed over the first gate electrode. The first dielectric structure has a lower portion and an upper portion disposed over the lower portion and wider than the lower portion. The second transistor includes: a second source and a second drain separated by a second distance greater than the first distance, a second semiconductor structure disposed between the second source and second drain, a second gate electrode disposed over the second semiconductor structure, and a second dielectric structure disposed over the second gate electrode. The second dielectric structure and the first dielectric structure have different material compositions.

    Multi-gate device and related methods
    165.
    发明授权
    Multi-gate device and related methods 有权

    公开(公告)号：US12166036B2

    公开(公告)日：2024-12-10

    申请号：US18341081

    申请日：2023-06-26

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Li-Yang Chuang ,  Jia-Chuan You ,  Kuo-Cheng Chiang ,  Chih-Hao Wang

    IPC: H01L27/088 ,  H01L21/762 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/66 ,  H01L29/78

    Abstract: A method of fabricating a semiconductor device includes providing a dummy structure having a plurality of channel layers, an inner spacer disposed between adjacent channels of the plurality of channel layers and at a lateral end of the channel layers, and a gate structure including a gate dielectric layer and a metal layer interposing the plurality of channel layers. The dummy structure is disposed at an active edge adjacent to an active region. A metal gate etching process is performed to remove the metal layer from the gate structure while the gate dielectric layer remains disposed at a channel layer-inner spacer interface. After performing the metal gate etching process, a dry etching process is performed to form a cut region along the active edge. The gate dielectric layer disposed at the channel layer-inner spacer interface prevents the dry etching process from damaging a source/drain feature within the adjacent active region.

    GATE-ALL-AROUND STRUCTURE AND METHODS OF FORMING THE SAME
    170.
    发明申请
    GATE-ALL-AROUND STRUCTURE AND METHODS OF FORMING THE SAME 有权

    公开(公告)号：US20240379857A1

    公开(公告)日：2024-11-14

    申请号：US18733499

    申请日：2024-06-04

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Pei-Hsun Wang ,  Chun-Hsiung Lin ,  Chih-Hao Wang

    IPC: H01L29/786 ,  H01L21/02 ,  H01L21/306 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66

    Abstract: Semiconductor device and the manufacturing method thereof are disclosed herein. An exemplary method comprises forming a fin over a substrate, wherein the fin comprises a first semiconductor layer and a second semiconductor layer including different semiconductor materials, and the fin comprises a channel region and a source/drain region; forming a dummy gate structure over the channel region of the fin and over the substrate; etching a portion of the fin in the source/drain region to form a trench therein, wherein a bottom surface of the trench is below a bottom surface of the second semiconductor layer; selectively removing an edge portion of the second semiconductor layer in the channel region such that the second semiconductor layer is recessed; forming a sacrificial structure around the recessed second semiconductor layer and over the bottom surface of the trench; and epitaxially growing a source/drain feature in the source/drain region of the fin.

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