公开(公告)号：US5079439A

公开(公告)日：1992-01-07

申请号：US655178

申请日：1991-02-12

Applicant: Frank Wanlass

Inventor： Frank Wanlass

IPC: H03K3/3565 ,  H03K19/003 ,  H03K19/0185

CPC classification number: H03K19/018521 ,  H03K19/00361 ,  H03K3/3565

Abstract: A TTL to CMOS buffer circuit includes a relatively high-speed first inverter path and a second relatively low-speed inverter path connected to the first path and effective to control the operation of the first path inverter so that short-duration positive- or negative-going noise pulses of amplitude up to 2.4 volts do not incorrectly affect the output level.

Abstract translation: TTL至CMOS缓冲电路包括相对高速的第一反相器路径和连接到第一路径的第二相对低速的反相器路径，并且有效地控制第一路径反相器的操作，使得短时间正或负 - 幅度高达2.4伏的噪声脉冲不会对输出电平造成不正确的影响。

公开(公告)号：US4899071A

公开(公告)日：1990-02-06

申请号：US227731

申请日：1988-08-02

Applicant: Lou Morales

Inventor： Lou Morales

IPC: H03K5/00 ,  H03K5/13 ,  H03K5/135 ,  H03L7/081

CPC classification number: H03L7/0805 ,  H03K5/133 ,  H03K5/135 ,  H03L7/0812 ,  H03K2005/00195

Abstract: A digital delay circuit that can be readily implemented in an integrated circuit is disclosed. The circuit includes a reference clock and two or more arrays of controlled delay elements. The reference clock is passed through one array of delay elements and the thus-delayed clock is compared to an undelayed clock in a phase detector or comparator the output of which is a control voltage. The latter is applied to the control inputs of each of the delay elements. The controlled delay elements may be in the form of buffers in which the delay is varible and controlled by the level of the control input.

Abstract translation: 公开了可以容易地在集成电路中实现的数字延迟电路。 该电路包括一个参考时钟和两个或更多个受控延迟元件阵列。 参考时钟通过一个延迟元件阵列，并将这样延迟的时钟与相位检测器或比较器中的未延迟时钟进行比较，其输出是一个控制电压。 后者被应用于每个延迟元件的控制输入。 受控的延迟元件可以是缓冲器的形式，其中延迟是可变的并且由控制输入的电平控制。

公开(公告)号：US4866706A

公开(公告)日：1989-09-12

申请号：US89976

申请日：1987-08-27

Applicant: James Christophersen ,  Sheldon Gilbert ,  Haig Sarkissian

Inventor： James Christophersen ,  Sheldon Gilbert ,  Haig Sarkissian

IPC: H04L12/417

CPC classification number: H04L12/417

Abstract: A controller is disclosed for use in a local area network preferably of the type having a token-passing protocol. The controller modifies the contents of a data packet or message as it moves on the network media, thereby to intercept, modify and redirect the data message to nodes other than the originally addressed node. In accordance with one embodiment of the invention, the controller is associated with a high-information node (e.g., a file server) connected in a network with a plurality of low-information nodes. The controller modifies the token address transmitted with the token packet from the high-information node after a number of data transmissions so that the token rather than being passed to the next node is returned to the high-information node, thereby allowing a plurality of successive data transmissions to be made in succession from the high-information node to one or more of the low-information nodes.

Abstract translation: 公开了一种用于局域网中的控制器，优选地具有令牌传递协议的类型。 控制器在网络媒体上移动时修改数据包或消息的内容，从而拦截，修改数据消息并将数据消息重定向到除原始寻址节点以外的节点。 根据本发明的一个实施例，控制器与连接在具有多个低信息节点的网络中的高信息节点（例如，文件服务器）相关联。 在多个数据传输之后，控制器利用来自高信息节点的令牌包发送的令牌地址修改，使得令牌而不是被传递到下一个节点的令牌返回到高信息节点，从而允许多个连续的 数据传输将从高信息节点连续地进行到一个或多个低信息节点。

公开(公告)号：US4845575A

公开(公告)日：1989-07-04

申请号：US106552

申请日：1987-10-06

Applicant: Richard E. Wahler

Inventor： Richard E. Wahler

IPC: G11B20/14

CPC classification number: G11B20/1403 ,  G11B20/1419

Abstract: A floppy disk data separator includes a phase lock loop which locks onto a clock signal that is synchronized to the data stream being read from the disk. The clock signal is derived from a sync counter which is reset each time a data bit is received from the disk. The output of the sync counter is an edge delayed by 1/4 of a bit time. The next edge of the clock occurs each 1/2 bit time after that until the next data bit is received. These clock signals are phase compared with clock signals produced in the phase lock loop to synchronize the clock to the disk data. In another aspect of the invention, the phase lock loop is operated in either a low-gain or high-gain mode.

Abstract translation: 软盘数据分离器包括锁相环，其锁定到与从盘读取的数据流同步的时钟信号。 时钟信号是从同步计数器导出的，每当从磁盘接收到数据位时，该计数器被复位。 同步计数器的输出是延迟1/4位时间的边沿。 时钟的下一个边沿出现在每个1/2位时间之后，直到接收到下一个数据位。 这些时钟信号与在锁相环中产生的时钟信号进行相位比较，以将时钟同步到磁盘数据。 在本发明的另一方面，锁相环以低增益或高增益模式工作。

公开(公告)号：US4796280A

公开(公告)日：1989-01-03

申请号：US118235

申请日：1987-11-06

Applicant: Richard Nesin ,  Tak-po Li

Inventor： Richard Nesin ,  Tak-po Li

IPC: H03K5/00 ,  G11B20/14 ,  H03M5/12 ,  H04L7/00 ,  H04L7/02 ,  H04L7/033 ,  H04L7/08 ,  H04L25/49

CPC classification number: H04L7/0331

Abstract: A data separator produces a reference clock from encoded data through the use of a digital logic that simulates the operation of an analog phase-locked loop. The digital phase-locked loop includes a counter oscillator that develops a period value which is incrementally modified in accordance with time variations in the new input data to maintain the regenerated data in proper phase relationship with the clock. The counter oscillator includes a zero-crossing counter which produces a reference clock signal to a clock and data regeneration circuit. The counter is incremented until its count is equal to the previously computed normal period value. This counter value is latched by a syncronized input data and represents the required period adjustment. As the data is syncronized with the reference clock the value of this adjustment approaches zero. The circuit also includes a digital low-pass filter that comprises a memory element that allows the new phase correction data to be added to the time-weighted previous period data.

Abstract translation: 数据分离器通过使用模拟模拟锁相环的操作的数字逻辑从编码数据产生参考时钟。 数字锁相环包括产生周期值的计数器振荡器，该周期值根据新的输入数据的时间变化而被增量地修改，以维持再生数据与时钟的正确的相位关系。 该计数器振荡器包括过零计数器，该计数器产生对时钟和数据再生电路的参考时钟信号。 计数器递增，直到其计数等于先前计算的正常周期值。 该计数器值由同步输入数据锁存，并表示所需的周期调整。 当数据与参考时钟同步时，此调整的值接近零。 电路还包括数字低通滤波器，其包括允许将新的相位校正数据添加到时间加权的前一周期数据的存储器元件。

公开(公告)号：US4719456A

公开(公告)日：1988-01-12

申请号：US709438

申请日：1985-03-08

Applicant: James D. Sproch ,  Morton B. Herman

Inventor： James D. Sproch ,  Morton B. Herman

IPC: G09G1/00 ,  G09G1/16

CPC classification number: G09G1/002

Abstract: A video dot intensity balancer for use in a video display system wherein information is represented by a series of logic bits in a video stream corresponding to dots to be displayed on a CRT is disclosed. Logic elements are coupled to the output of a bit generator for comparing adjacent bits and outputting an information-defining signal wherein a single information-defining bit never stands alone. In this manner, apparent intensity imbalances on the video screen are eliminated.

Abstract translation: 公开了一种在视频显示系统中使用的视频点强度平衡器，其中信息由对应于要显示在CRT上的点的视频流中的一系列逻辑位表示。 逻辑元件耦合到比特发生器的输出，用于比较相邻比特并输出信息定义信号，其中单个信息定义比特永远不会独立。 以这种方式，消除了视频屏幕上的视在强度不平衡。

公开(公告)号：US4625321A

公开(公告)日：1986-11-25

申请号：US737060

申请日：1985-05-23

Applicant: Henry W. Pechar ,  Tak P. Li

Inventor： Henry W. Pechar ,  Tak P. Li

IPC: G11B20/14 ,  H03K5/19 ,  H03K21/02 ,  H03M5/06 ,  H04K1/02

CPC classification number: G11B20/1423 ,  G11B20/1403 ,  G11B20/1419

Abstract: A circuit is disclosed for separating clock and data signals from a combined data-clock stream derived from a disk. The circuit includes two memories or shift registers which sample the incoming data at alternate portions of a reference clock. The outputs of the registers are applied to a decoder which identifies which of the two registers contains the data portion and which contains the clock portion with the missing clock pattern. That determination, in turn, controls the generation of the synchronization signal for the circuit and also establishes a control signal that selects data from the other of the registers.

Abstract translation: 公开了一种用于将时钟和数据信号与从盘导出的组合数据时钟流分离的电路。 该电路包括两个存储器或移位寄存器，用于在参考时钟的交替部分对输入数据进行采样。 寄存器的输出被应用于识别两个寄存器中的哪一个包含数据部分并且包含具有丢失的时钟模式的时钟部分的解码器。 该决定又控制电路的同步信号的产生，并且还建立从另一个寄存器中选择数据的控制信号。

公开(公告)号：US4547684A

公开(公告)日：1985-10-15

申请号：US525286

申请日：1983-08-22

Applicant: Henry Pechar

Inventor： Henry Pechar

IPC: H03K5/151 ,  H03K5/15 ,  H03K3/353 ,  H03K19/094

CPC classification number: H03K5/1515

Abstract: A clock generator for producing nonoverlapping clocks from an input clock includes an MOS depletion-mode device receiving the input clock at an input. The output of the depletion-mode device, which constitutes one of the clocks, is also applied to one input of a NOR gate, the other input of which is the input clock. The output of the NOR gate is the second clock.

Abstract translation: 用于从输入时钟产生非重叠时钟的时钟发生器包括在输入端接收输入时钟的MOS耗尽模式器件。 构成时钟之一的耗尽型器件的输出也被施加到NOR门的一个输入，其另一个输入是输入时钟。 NOR门的输出是第二个时钟。

公开(公告)号：US4516040A

公开(公告)日：1985-05-07

申请号：US502724

申请日：1983-06-09

Applicant: John M. Zapisek ,  Gus Giulekas

Inventor： John M. Zapisek ,  Gus Giulekas

IPC: H03K19/177 ,  G06F7/48 ,  H03K19/094

CPC classification number: H03K19/17708

Abstract: A programmable logic array includes a plurality of MOS switching devices formed at preselected locations in an array made up of input and output lines and intersecting product term lines. One group of MOS devices constituting the "AND" plane arranged at the intersections of the input lines and product term lines performs a logic operation on input signals to the array and outputs logic signals onto the product term lines. A second group of MOS devices constituting the "OR" plane located at the intersections of the output lines and product term lines receives the outputs of the "AND" plane devices and performs a logic operation on those signals to produce a set of output signals that are presented at the outputs of the array for use by an external device. The merged plane array of the invention advantageously includes dual-gate MOS devices as switching elements to reduce the capacitance on the product term lines and output lines and thereby to increase the operating speed of the array. The input and output lines and related MOS devices of the array rather than being arranged in physically separate and distant input "AND" and output "OR" planes, as in the prior art, are interspersed or merged with one another so as to reduce the amount of interconnect required between the logic array and an external device which provides the inputs to the array and receives the outputs therefrom.

Abstract translation: 可编程逻辑阵列包括在由输入和输出线构成的阵列中的预选位置处形成的多个MOS开关器件和相交的乘积项线。 布置在输入线和乘积项线的交点处的“AND”平面的一组MOS器件对阵列的输入信号执行逻辑运算，并将逻辑信号输出到乘积项线上。 构成位于输出线和产品项线的交点处的“OR”平面的第二组MOS器件接收“AND”平面器件的输出，并对这些信号执行逻辑运算，以产生一组输出信号， 呈现在阵列的输出端以供外部设备使用。 本发明的合并平面阵列有利地包括作为开关元件的双栅MOS器件，以减少产品项线和输出线上的电容，从而增加阵列的工作速度。 阵列的输入和输出线路和相关的MOS器件不是如现有技术那样被散布或合并，而不是布置在物理上分离的和远离的输入“AND”中并输出“OR”平面，以便减少 在逻辑阵列和向阵列提供输入并从其接收输出的外部设备之间所需的互连量。

公开(公告)号：US10749994B2

公开(公告)日：2020-08-18

申请号：US15786224

申请日：2017-10-17

Applicant: Microchip Technology Incorporated

Inventor： Hariramanathan Ramakrishnan ,  Bryan A. Whitehead ,  Maksim A. Azarov ,  Neil A. Winchester ,  William R. Chiechi

IPC: H04L29/06 ,  H04L12/861 ,  G06F15/16 ,  G06F15/163 ,  H04N21/239 ,  H04N21/41 ,  H04L29/12

Abstract: A network device (ND) includes a first interface controller operable to transfer data between the ND and a host processing unit (host), a second interface controller operable to transfer data between the ND and the host, a network interface configured to interface the ND with a network, and a control unit operable to: receive incoming data from the network, process the incoming data, and transmit the processed incoming data to the host through the second interface controller; or, receive outgoing data from the host through the second interface controller, process the received outgoing data, and transmit the processed outgoing data to the network. The first interface controller, the control unit, and the network interface are together operable to enable the host to transmit and/or receive other data to and/or from the network and the first interface controller. The host and the control unit share a same network address.