Abstract:
Systems and methods for improved chip device performance are discussed herein. An exemplary chip device for use in an integrated circuit comprises a bottom and a top opposite the bottom. The chip device comprises a through-chip device interconnect and a clearance region. The through-chip device interconnect is configured to provide an electrical connection between a ground plane trace on the bottom and a chip device path on the top of the chip device. The clearance region on the bottom of the chip device comprises an electrically conductive substance. The size and shape of the clearance region assist in impedance matching. The chip device path on the top of the chip device may further comprise at least one tuning stub. The size and shape of the at least one tuning stub also assist in impedance matching.
Abstract:
A system comprises a wheel assembly including a wheel shaft and first and second wheels rotationally coupled to the wheel shaft; a first bracket coupled to a device rack and including a first open slot, the first open slot including a receiving portion configured to receive the wheel shaft at a first position, a delivery portion configured to deliver the wheel shaft upon tilting the rack forwards, and a locking portion configured to secure the wheel shaft upon tilting the rack backwards; and a second bracket configured to be coupled to the rack on a second side and including a second open slot, the second open slot including a receiving portion configured to receive the wheel shaft at a second position, a delivery portion configured to deliver the wheel shaft upon tilting the rack forwards, and a locking portion configured to secure the wheel shaft upon tilting the rack backwards.
Abstract:
An example method comprises receiving, by a first PHY of a first transceiver, a timing packet, timestamping, by the first transceiver, the timing packet and providing the timing packet to a first intermediate node, determining a first offset between the first intermediate node and the first transceiver, updating a first field within the timing packet with the first offset between the first intermediate node and the first transceiver, the offset being in the direction of the second transceiver, receiving the timing packet by a second transceiver, the timing packet including the first field, information within the first field being at least based on the first offset, determining a second offset between the second transceiver and an intermediate node that provided the timing packet to the second transceiver and correcting a time of the second transceiver based on the information within the first field and the second offset.
Abstract:
A first layer one link aggregation master comprises a first port coupled to receive customer traffic; a first channel; a second channel; an aggregation engine coupled to the first and second channels; a first switch circuit coupled to the first port and to the first channel, and configured to communicate the customer traffic from the first port over the first channel to the aggregation engine, the aggregation engine including a splitter circuit configured to use layer one information to segment at least a portion of the customer traffic into a first virtual container and a second virtual container, the aggregation engine further including an encapsulation circuit configured to encapsulate the second virtual container using Ethernet standards for transport over the second channel; a radio access card configured to generate an air frame based on the first virtual container for wireless transmission over a first wireless link of a link aggregation group to the receiver; and a second switch circuit coupled to the second channel, and configured to communicate the Ethernet-encapsulated second virtual container over an Ethernet cable to a slave for wireless transmission over a second wireless link of the link aggregation group to the receiver.
Abstract:
A frame error correction circuit may identify and correct errors in data frames provided to a receiver as part of a diversity communications scheme. The frame error correction circuit may further align the data frames so that the data frames can be compared. The frame error correction circuit may perform a bit-wise comparison of the data frames and identify inconsistent bit positions where bits in the data frames differ from one another. Once inconsistent bit positions have been identified, the frame error correction circuit may access a permutation table of permutations of bits at the inconsistent bit positions. In some implementations, the frame error correction circuit uses the permutation table to reassemble permutations of the data frames. In various implementations, the frame error correction circuit performs a CRC of each permutation of the data frames, and provides a valid permutation to a network.
Abstract:
An example system comprises a first antenna and a modem. The first antenna is configured to receive a signal from a transmitting radio frequency unit. The signal includes data and a known sequence. The modem is configured to retrieve the known sequence from the signal, transform the known sequence and the data into a frequency domain, calculate averages of groups of neighboring frequency points in the frequency domain to reduce the effect of nonlinear noise in the signal, the neighboring frequency points corresponding to the preamble in the frequency domain, compare the calculated averages to an expected frequency response in the frequency domain, determine a correction filter to apply to the data based on the comparison, apply the correction filter on the data in the frequency domain to create corrected data, transform the corrected data from the frequency domain to the time domain, and provide the data.
Abstract:
Rapid failure detection and recovery in wireless communication networks is needed in order to meet, among other things, carrier class Ethernet transport channel standards. Thus, resilient wireless packet communications is provided using a hardware-assisted rapid transport channel failure detection algorithm and a Gigabit Ethernet data access card with an engine configured accordingly. In networks with various topologies, this is provided in combination with their existing protocols, such as rapid spanning tree and link aggregation protocols, respectively.
Abstract:
In some embodiments, a first RF signal is received at a wireless repeater, a signal quality is determined based on the first RF signal, the signal quality is analyzed based on a parameter, an operation mode is auto selected based on analysis of the signal quality, and a second RF signal based on the first RF signal is generated for transmission according to the selected operation mode. Under one mode, a first RAC of the wireless may generate data based on a first IF signal downconverted from a first RF signal. Based on the data, a second RAC of the wireless repeater may generate a second IF signal, which can be used to generate a second RF signal for transmission. Under another mode, the first RAC may provide the IF signal to the second RAC, which provides the IF signal for generation of the second RF signal.
Abstract:
In some embodiments, a system comprises a clock, a root node, a radio channel network, and first and second child nodes. The clock may be configured to generate a clock signal. The root node may be configured to generate a first frame including a first payload and a first overhead and generate a second frame including a second payload and a second overhead. The first and second overheads may comprise a synchronization value based on the clock signal. The radio channel network may be in communication with the root node for transmitting the first and second frames. Each first and second child nodes may be configured to perform clock recovery including frequency synchronization using the synchronization value and a respective phase-lock loop.
Abstract:
Various embodiments are directed toward systems and method for manufacturing low cost passive waveguide components. For example, various embodiments relate to low cost manufacturing of passive waveguide components, including without limitation, waveguide filters, waveguide diplexers, waveguide multiplexers, waveguide bends, waveguide transitions, waveguide spacers, and antenna adapters. Some embodiments comprise manufacturing a passive waveguide component by creating a non-conductive structure using a low cost fabrication technology, such as injection molding or three-dimensional (3D) printing, and then forming a conductive layer over the non-conductive structure such that the conductive layer creates an electrical feature of the passive waveguide component.