公开(公告)号：US09686609B1

公开(公告)日：2017-06-20

申请号：US14320104

申请日：2014-06-30

Applicant: Avnera Corporation

Inventor： Chris O'Connor ,  Xudong Zhao

IPC: H04R1/10 ,  H04R3/12

CPC classification number: H04R3/12 ,  G10L19/012 ,  H04R1/1041 ,  H04R5/04 ,  H04R29/001 ,  H04R2420/05 ,  H04R2460/03

Abstract: A low power, digital audio interface includes support for variable length coding depending on content of the audio data sent from the interface. A particularized coding system is implemented that uses techniques of silence detection, dynamic scaling, and periodic encoding to reduce sent data to a minimum. Other techniques include variable packet scaling based on an audio sample rate. Differential signaling techniques are also used. The digital audio interface may be used in a headphone interface to drive digital headphones. A detector in the interface may detect whether digital or analog headphones are coupled to a headphone jack and drive the headphone jack accordingly.

公开(公告)号：US09621336B1

公开(公告)日：2017-04-11

申请号：US14471324

申请日：2014-08-28

Applicant: Avnera Corporation

Inventor： Samuel J. Peters, II ,  Eric P. Etheridge ,  Victor Lee Hansen ,  Alexander C. Stange

IPC: H04L7/033

CPC classification number: H04L7/033 ,  G06F13/4295 ,  H04L7/0029 ,  H04L7/02

Abstract: A system and a technique for recovering data from an input data stream without synchronization of an input sampling circuit to the input data stream determines a count of incoming samples (or frames) without generating a signal that is frequency-locked to the input data stream. A first clock is generated comprising a frequency that is greater than or equal to an expected frequency of the input data stream. A sample count is incremented in response to a sample received in the input data stream, and is decremented in response to a second clock signal. The second clock is generated from the first clock signal by passing the first clock signal if the sample count of the sample counter does not equal a predetermined sample count value and by blocking the first clock signal if the sample count equals the predetermined sample count value.

公开(公告)号：US20170013345A1

公开(公告)日：2017-01-12

申请号：US14850859

申请日：2015-09-10

Applicant: Avnera Corporation

Inventor： Amit Kumar ,  Eric Sorensen ,  Shankar Rathoud

IPC: H04R1/10

CPC classification number: H04R1/1041 ,  G10K11/178 ,  G10K11/17855 ,  G10K2210/1081 ,  G10K2210/3021 ,  H04R1/1083 ,  H04R3/00 ,  H04R29/00 ,  H04R2410/05 ,  H04R2460/03

Abstract: A headphone detector including a headphone and a processor. The headphone has a microphone and a speaker, and the microphone is configured to generate an audio signal based on an output of the speaker. The processor is configured to receive the audio signal, determine a characteristic of the audio signal, and assess whether the headphone is on ear or off ear based on a comparison of the characteristic to a threshold. In another aspect, an off-ear detection (OED) system includes a headphone and an OED processor. The headphone has a speaker, a feedforward microphone, and a feedback microphone. The OED processor is configured to determine whether the headphone is off ear or on ear, based at least in part on a headphone audio signal, a feedforward microphone signal, and a feedback microphone signal.

Abstract translation: 一种耳机检测器，包括耳机和处理器。 耳机具有麦克风和扬声器，麦克风被配置为基于扬声器的输出产生音频信号。 处理器被配置为接收音频信号，确定音频信号的特性，并且基于特征与阈值的比较来评估耳机是耳朵还是耳朵。 在另一方面，一种耳朵检测（OED）系统包括耳机和OED处理器。 耳机具有扬声器，前馈麦克风和反馈麦克风。 OED处理器被配置为至少部分地基于耳机音频信号，前馈麦克风信号和反馈麦克风信号来确定耳机是否脱离耳朵或耳朵。

公开(公告)号：US09525388B1

公开(公告)日：2016-12-20

申请号：US14323657

申请日：2014-07-03

Applicant: Avnera Corporation

Inventor： Ali Hadiashar ,  Wai Lang Lee

IPC: H03G3/20 ,  H03F3/183 ,  H03F3/45

CPC classification number: H03F3/183 ,  H03F1/26 ,  H03F3/187 ,  H03F3/45475 ,  H03F3/45941 ,  H03F3/45968 ,  H03F3/68 ,  H03F2200/03 ,  H03F2200/372 ,  H03F2203/45418 ,  H03F2203/45522 ,  H03F2203/45531

Abstract: A new compensation system for an audio input reduces noise by matching feedback ratios in the positive and negative paths. A variable resistance network allows for fine control of resistance trimming in one of the signal paths, which allows for compensation between tolerance of resistors that are external to an integrated circuit and those that are internal to the integrated circuit.

Abstract translation: 用于音频输入的新补偿系统通过匹配正和负路径中的反馈比来降低噪声。 可变电阻网络允许精细控制信号路径之一的电阻微调，这允许在集成电路外部的电阻器的容差与集成电路内部的电阻器之间进行补偿。

公开(公告)号：US08643525B1

公开(公告)日：2014-02-04

申请号：US13733301

申请日：2013-01-03

Applicant: Avnera Corporation

Inventor： Jianping Wen ,  Amit Kumar ,  Garry N. Link ,  Wai Laing Lee

IPC: H03M1/66

CPC classification number: H03M1/067 ,  H03M1/74 ,  H03M3/502

Abstract: A system and method dynamically selects digital-to-analog (DAC) circuit elements to provide a True differential-output delta-sigma (ΔΣ) DAC. The sign and magnitude of a received N-bit input code is determined. If the input code comprises a positive value, m+r circuit elements are selected from a plurality of circuit elements by a positive element selector, in which comprises a number of rotational elements, and r circuit elements are selected by a negative element selector. Each selected circuit element comprises a circuit element that was not selected for an immediately preceding received input code and has a corresponding minimum usage count value. If the input digital code comprises a negative value, m+r circuit elements are selected by the negative element selector, and r circuit elements are selected by the positive element selector. The circuit elements are capable of being configured as positive or negative circuit elements.

Abstract translation: 一种系统和方法动态地选择数模（DAC）电路元件，以提供真差分输出Δ-Σ（DeltaSigma）DAC。 确定接收到的N位输入代码的符号和大小。 如果输入代码包括正值，则通过正元件选择器从多个电路元件中选择m + r个电路元件，其中包括多个旋转元件，并且r个电路元件由负元件选择器选择。 每个所选择的电路元件包括未被选择用于紧接在前的接收输入代码并且具有对应的最小使用计数值的电路元件。 如果输入数字代码包含负值，则由负选择器选择m + r个电路元件，并且通过正元件选择器选择r个电路元件。 电路元件能够被配置为正或负电路元件。