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    Image forming apparatus
    174.
    发明授权
    Image forming apparatus 有权
    图像形成装置

    公开(公告)号：US09535383B2

    公开(公告)日：2017-01-03

    申请号：US13087482

    申请日：2011-04-15

    Applicant: Kiyoshi Inoue

    Inventor： Kiyoshi Inoue

    IPC: G03G15/36 ,  H04N1/00 ,  H04N1/38 ,  H04N1/387 ,  G03G15/00

    CPC classification number: B41J13/0009 ,  G03G15/36 ,  G03G15/50 ,  G03G15/502 ,  G03G2215/00569 ,  G03G2215/00582 ,  G06F3/1218 ,  G06F3/1219 ,  H04N1/00002 ,  H04N1/00015 ,  H04N1/00031 ,  H04N1/00053 ,  H04N1/00063 ,  H04N1/3873 ,  H04N2201/0094

    Abstract: When trial printing is executed in a repeat printing mode, trial printing is performed in size of an image of one piece in a layout in which a plurality of images are supposed to be printed in the repeat printing mode normally. A user who has checked a finished state of the trial printing sets, when the finished state is in a desired state, the recording paper on which the trial printing is performed to the paper feed portion again and executes the repeat printing. Thereby, in a blank space excluding a print image which is printed with a first time trial printing, a scheduled quantity of a plurality of images are repeatedly printed.

    Abstract translation: 当在重复打印模式下执行试打印时，在重复打印模式中正常地应该以多张图像被打印的布局中的一个图像的大小执行试打印。 当完成状态处于期望状态时，​​已经检查了试纸打印的完成状态的用户再次对进纸部分进行了试纸打印的记录纸，并执行了重复打印。 由此，除了在第一次试打印上打印的打印图像之外的空白空间中，重复打印多张图像的调度量。

    SEMICONDUCTOR MEMORY DEVICE HAVING FAULTY CELLS
    175.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE HAVING FAULTY CELLS 失效
    具有故障细胞的半导体存储器件

    公开(公告)号：US20120213002A1

    公开(公告)日：2012-08-23

    申请号：US13298548

    申请日：2011-11-17

    Applicant: Kunihiro KATAYAMA ,  Takayuki TAMURA ,  Satoshi WATATANI ,  Kiyoshi INOUE ,  Shigemasa SHIOTA ,  Masashi NAITO

    Inventor： Kunihiro KATAYAMA ,  Takayuki TAMURA ,  Satoshi WATATANI ,  Kiyoshi INOUE ,  Shigemasa SHIOTA ,  Masashi NAITO

    IPC: G11C29/00 ,  G11C16/06

    CPC classification number: G11C16/349 ,  G11C29/76 ,  G11C29/88

    Abstract: In response to a read command received by a system interface unit for accessing a plurality of blocks of data stored in said non-volatile semiconductor memory, a controller carries out selective read operations of blocks of data to two memories from the non-volatile semiconductor memory. The controller also carries out parallel operations of data transferring a first block of data, which has already been subjected to error detection and error correction operations by an error correction unit, from one of the two memories to a host system via said system interface unit and of data transferring of a second block of data to be subjected to the error detection and error correction operation, from said non-volatile semiconductor memory to the other of the two memories.

    Abstract translation: 响应于由用于访问存储在所述非易失性半导体存储器中的多个数据块的系统接口单元接收到的读取命令，控制器对来自非易失性半导体存储器的两个存储器执行数据块的选择性读取操作 。 所述控制器还执行数据的并行操作，所述数据传输已经经过错误校正单元的错误检测和纠错操作的第一数据块经由所述系统接口单元从所述两个存储器之一传送到主机系统，并且 将要进行错误检测和纠错操作的第二数据块的数据传输从所述非易失性半导体存储器传输到两个存储器中的另一个。

    SEMICONDUCTOR MEMORY HAVING ELECTRICALLY ERASABLE AND PROGRAMMABLE SEMICONDUCTOR MEMORY CELLS
    176.
    发明申请
    SEMICONDUCTOR MEMORY HAVING ELECTRICALLY ERASABLE AND PROGRAMMABLE SEMICONDUCTOR MEMORY CELLS 有权
    具有电可擦除和可编程半导体存储器单元的半导体存储器

    公开(公告)号：US20120127792A1

    公开(公告)日：2012-05-24

    申请号：US13363400

    申请日：2012-02-01

    Applicant: Kunihiro KATAYAMA ,  Takayuki Tamura ,  Kiyoshi Inoue

    Inventor： Kunihiro KATAYAMA ,  Takayuki Tamura ,  Kiyoshi Inoue

    IPC: G11C16/10

    CPC classification number: G11C16/28 ,  G11C11/5621 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/10 ,  G11C16/30 ,  G11C2211/5621 ,  G11C2211/5632 ,  G11C2211/5634 ,  G11C2211/5641 ,  G11C2211/5642

    Abstract: In a nonvolatile memory apparatus, a system bus receives address, command, and/or control signals. Memory cells store bits of data by shifting a threshold voltage to one of plural ranges. In writing a first page, the threshold voltage of a first memory cell remains in a first range or shifts into a second range. In writing a second page, the threshold voltage remains in the first or second voltages, or shifts into a third range from the first range or into a fourth range from the second range. Before writing the second page, the memory reads data from the first memory cell for generating the second page writing data. A shifting direction of the threshold voltage from the first to the second range is the same as a shifting direction from the first to the third range.

    Abstract translation: 在非易失性存储装置中，系统总线接收地址，命令和/或控制信号。 存储单元通过将阈值电压移位到多个范围之一来存储数据位。 在写入第一页时，第一存储器单元的阈值电压保持在第一范围或者移位到第二范围。 在写第二页时，阈值电压保持在第一或第二电压中，或者从第二范围移动到从第一范围到第四范围的第三范围。 在写入第二页之前，存储器从第一存储器单元读取用于生成第二页写入数据的数据。 从第一到第二范围的阈值电压的移动方向与从第一到第三范围的移动方向相同。

    Semiconductor memory having electrically erasable and programmable semiconductor memory cells
    178.
    发明授权
    Semiconductor memory having electrically erasable and programmable semiconductor memory cells 有权
    具有电可擦除和可编程的半导体存储器单元的半导体存储器

    公开(公告)号：US07881111B2

    公开(公告)日：2011-02-01

    申请号：US12504307

    申请日：2009-07-16

    Applicant: Kunihiro Katayama ,  Takayuki Tamura ,  Kiyoshi Inoue

    Inventor： Kunihiro Katayama ,  Takayuki Tamura ,  Kiyoshi Inoue

    IPC: G11C16/04

    CPC classification number: G11C16/28 ,  G11C11/5621 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/10 ,  G11C16/30 ,  G11C2211/5621 ,  G11C2211/5632 ,  G11C2211/5634 ,  G11C2211/5641 ,  G11C2211/5642

    Abstract: An electrically alterable non-volatile multi-level memory device and a method of operating such a device, which includes setting a status of at least one of the memory cells to one state selected from a plurality of states including at least first to fourth level states, in response to information to be stored in the one memory cell, and reading the status of the memory cell to determine whether the read out status corresponds to one of the first to fourth level states by utilizing a first reference level set between the second and third level states, a second reference level set between the first and second level states and a third reference level set between the third and fourth level states.

    Abstract translation: 一种可电气可变的非易失性多级存储器件和操作这种器件的方法，其包括将至少一个存储器单元的状态设置为从包括至少第一至第四电平状态的多个状态中选择的一种状态 响应于要存储在一个存储器单元中的信息，并且通过利用在第二和第二电平状态之间设置的第一参考电平来读取存储单元的状态来确定读出状态是否对应于第一至第四电平状态之一 第三电平状态，在第一和第二电平状态之间设置的第二参考电平和在第三和第四电平状态之间设置的第三参考电平。

    SEMICONDUCTOR MEMORY HAVING ELECTRICALLY ERASABLE AND PROGRAMMABLE SEMICONDUCTOR MEMORY CELLS
    179.
    发明申请
    SEMICONDUCTOR MEMORY HAVING ELECTRICALLY ERASABLE AND PROGRAMMABLE SEMICONDUCTOR MEMORY CELLS 有权
    具有电可擦除和可编程半导体存储器单元的半导体存储器

    公开(公告)号：US20100014351A1

    公开(公告)日：2010-01-21

    申请号：US12504307

    申请日：2009-07-16

    Applicant: Kunihiro KATAYAMA ,  Takayuki Tamura ,  Kiyoshi Inoue

    Inventor： Kunihiro KATAYAMA ,  Takayuki Tamura ,  Kiyoshi Inoue

    IPC: G11C16/04 ,  G11C7/00

    CPC classification number: G11C16/28 ,  G11C11/5621 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/10 ,  G11C16/30 ,  G11C2211/5621 ,  G11C2211/5632 ,  G11C2211/5634 ,  G11C2211/5641 ,  G11C2211/5642

    Abstract: An electrically alterable non-volatile multi-level memory device and a method of operating such a device, which includes setting a status of at least one of the memory cells to one state selected from a plurality of states including at least first to fourth level states, in response to information to be stored in the one memory cell, and reading the status of the memory cell to determine whether the read out status corresponds to one of the first to fourth level states by utilizing a first reference level set between the second and third level states, a second reference level set between the first and second level states and a third reference level set between the third and fourth level states.

    Abstract translation: 一种可电气可变的非易失性多级存储器件和操作这种器件的方法，其包括将至少一个存储器单元的状态设置为从包括至少第一至第四电平状态的多个状态中选择的一种状态 响应于要存储在一个存储器单元中的信息，并且通过利用在第二和第二电平状态之间设置的第一参考电平来读取存储单元的状态来确定读出状态是否对应于第一至第四电平状态之一 第三电平状态，在第一和第二电平状态之间设置的第二参考电平和在第三和第四电平状态之间设置的第三参考电平。

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