Abstract:
The present invention provides a STATS inhibitor containing as an active ingredient, a quinolinecarboxamide derivative represented by the formula (I) (in the formula, W represents a bond or an alkylene chain; X represents O, S, or NR34; and R1 to R8 and R34 each represent H, halogen, alkyl, phenyl, furyl, thienyl, or the like), or a pharmacologically acceptable salt thereof.
Abstract:
Provided is a 1,3,4-oxadiazole-2-carboxamide compound which has STAT3 inhibitory activity and is useful as an anticancer agent. Provided is a 1,3,4-oxadiazole-2-carboxamide compound represented by formula (I) or a pharmacologically acceptable salt thereof (in the formula, Ar represents a furyl group or the like; R1 represents a hydrogen atom or the like; and —X—Y represents a diaryl group such as a biphenyl group).
Abstract translation:提供具有STAT3抑制活性并可用作抗癌剂的1,3,4-恶二唑-2-甲酰胺化合物。 提供由式(I)表示的1,3,4-恶二唑-2-甲酰胺化合物或其药学上可接受的盐(在该式中,Ar表示呋喃基等; R 1表示氢原子等; -X-Y表示二苯基等二芳基)。
Abstract:
When a predetermined region of a target volume is divided into multiple layers in a depth direction of particle beams and particle beams are irradiated, dose calibration is carried out separately for the divided layers.
Abstract:
A semiconductor device manufacturing method is a method of forming a semiconductor device that includes a cell part that includes plural transistor cells in each of which a gate of a trench type is formed in a semiconductor layer, and diffused layers are formed on both sides of the gate, and a guard ring part that surrounds the cell part. The semiconductor device manufacturing method includes forming an interlayer dielectric film on a surface of the semiconductor layer in which the gate and the diffused layers are formed; reducing a thickness of the interlayer dielectric film formed in the cell part through etch back; forming a contact part having a shape of a hole or a groove in the interlayer dielectric film at a position above the diffused layer; and forming a metal film on the interlayer dialectic film.
Abstract:
[Task] A constant-modulus alloy, which has a low saturation magnetic flux density to provide weakly magnetic properties, a high Young's modulus, a low temperature coefficient of Young's modulus, and high hardness, is provided. A hairspring, a mechanical driving apparatus and a watch and clock, in which the alloy is used, are provided.[Means for Solution]The alloy consists essentially of, by atomic weight ratio, 20 to 40% Co and 7 to 22% Ni, with the total of Co and Ni being 42.0 to 49.5%, 5 to 13% Cr and 1 to 6% Mo, with the total of Cr and Mo being 13.5 to 16.0%, and with the balance being essentially Fe (with the proviso that Fe is present in an amount of 37% or more) and inevitable impurities. The alloy is heated to a temperature of 1100 degrees C. or higher and lower than the melting point, followed by cooling. The alloy is subsequently subjected to repeated wiredrawing and intermediate annealing at 800 to 950 degrees C., thereby forming a wire at a working ratio of 90% or more. The resultant wire has a fiber structure having a fiber axis. The wire is subsequently cold rolled at a rolling reduction of 20% or more, thereby obtaining a sheet, followed by heating the sheet at a temperature of 580 to 700 degrees C. The obtained magnetically insensitive, highly hard, constant modulus alloy has a {110} texture. 2500 to 3500 G of saturation flux density, (−5˜+5)×10−5 degrees C−1 of temperature coefficient of Young's modulus as measured at 0 to 40 degrees C., and 350 to 550 of Vickers hardness
Abstract:
A method, an apparatus, and a computer program are provided to utilize built-in self test (BIST) latches for multiple purposes. Conventionally, BIST latches are single purpose. Hence, separate latches are utilized for array built-in self test (ABIST) and logic built-in self test (LBIST) operations. By having the separate latches, though, a substantial amount area is lost. Therefore, to better utilize the latches and the area, ABIST latches are reconfigured to utilize some previously unused ports to allow for multiple uses for the latches, such as for LBIST.
Abstract:
A battery pack is provided. For example, the battery pack includes a box-shaped or plate-shaped battery pack. The battery pack has a hard outer jacket member, a box-shaped or plate-shaped battery element, a cover, and a circuit board. The hard outer jacket member has a first opening and a second opening formed at both ends. The box-shaped or plate-shaped battery element is contained in the outer jacket member and has electrode terminals. The cover is molded from resin and is fitted to the first opening. The circuit board is connected to the electrode terminal leads and contained in the cover. At least the electrode terminal leads extends from the first opening. The cover has concave portions on both ends of one longer side. The outer jacket member has cut portions that expose at least the concave portions of the cover. At least a longer side of the cover and the outer jacket member are heat-adhered.
Abstract:
Provided is a carbon nanotube field effect transistor manufacturing method wherein carbon nanotube field effect transistors having excellent stable electric conduction property are manufactured with excellent reproducibility. After arranging carbon nanotubes to be a channel on a substrate, the carbon nanotubes are covered with an insulating protection film. Then, a source electrode and a drain electrode are formed on the insulating protection film. At this time, a contact hole is formed on the protection film, and the carbon nanotubes are connected with the source electrode and the drain electrode. Then, a wiring protection film, a conductive film and a plasma CVD film are sequentially formed on the insulating protection film, the source electrode and the drain electrode. In the field effect transistor thus manufactured, since the carbon nanotubes to be the channel are not contaminated and not damaged, excellent stable electric conductive property is exhibited.
Abstract:
A DC-DC converter control circuit includes: a slope signal generation circuit that generates a reference voltage by superimposing a slope voltage onto a standard voltage; a comparator that performs comparison of the reference voltage with an output voltage and generates a signal according to a result of the comparison; an oscillator that generates a pulse signal with a substantially constant cycle; and a control signal generation circuit that generates a control signal that turns on a switch based on a comparator output signal and turns off the switch based on the pulse signal.
Abstract:
An image forming apparatus is provided. The image forming apparatus includes, a carrier element, an image forming unit, a patch mark generation unit, a specular reflected light detection unit that detects light irradiated onto the carrier element by the irradiation unit and specularly-reflected by the carrier element or patch marks, and a diffuse reflected light detection unit that detects the light irradiated onto the carrier element by the irradiation unit and diffusely-reflected by the carrier element or the patch marks. Additionally, the image forming apparatus includes, a correction unit that corrects at least one of a value detected by the specular reflected light detection unit and the diffuse reflected light detection unit, a correction condition determination unit that determines correction conditions for the correction unit, and a density calculation unit that calculates a density of a patch mark.