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公开(公告)号：US20230110870A1
公开(公告)日：2023-04-13
申请号：US17490976
申请日：2021-09-30
Inventor： Laura Capecchi , Marcella Carissimi , Marco Pasotti , Vikas Rana , Vivek Tyagi
Abstract: A system and method for operating a memory cell is provided. A non-volatile memory storage device includes an array of memory cells of differential or single-ended type. In an embodiment, a regulator is coupled to a sense amplifier. The regulator is configured to generate a voltage to gate terminals of one or two transistors of the sense amplifier. In the differential type, the voltage is generated such that the first bias current and the second bias current have a current value equal to the sum of a maximum current flowing in a memory cell being in a RESET state and a fixed current. In the single-ended type, the regulated voltage is generated such that the first bias current and the second bias current have a current value equal to the sum of a fixed current and the reference current generated by the reference current source across temperature.
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公开(公告)号：US20230091970A1
公开(公告)日：2023-03-23
申请号：US18052514
申请日：2022-11-03
Applicant: STMICROELECTRONICS INTERNATIONAL N.V.
Inventor： Tushar SHARMA , Tanmoy ROY , Shishir KUMAR
IPC: H01L27/11 , G11C5/06 , G11C11/412 , H01L27/02 , G11C8/16 , G11C11/417
Abstract: The present disclosure is directed to a circuit layout of a dual port static random-access-memory (SRAM) cell. The memory cell includes active regions in a substrate, with polysilicon gate electrodes on the active regions to define transistors of the memory cell. The eight transistor (8T) memory cell layout includes a reduced aspect ratio and non-polysilicon bit line discharge path routing by positioning an active region for the first port opposite an active region for the second port and consolidating power line nodes at a central portion of the memory cell.
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公开(公告)号：US20230090782A1
公开(公告)日：2023-03-23
申请号：US17931863
申请日：2022-09-13
Applicant: STMicroelectronics International N.V.
Inventor： Anand KUMAR , Nitin JAIN
IPC: H03B5/36
Abstract: A low power crystal oscillator circuit having a high power part and a low power part. Oscillation is initialized using the high power part. Once the crystal is under stable oscillation, the circuit switches to the low power part and continue operation for a long duration.
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公开(公告)号：US11575254B2
公开(公告)日：2023-02-07
申请号：US17095652
申请日：2020-11-11
Inventor： Manoj Kumar , Ravinder Kumar , Nicolas Demange
Abstract: An integrated circuit includes an overvoltage protection circuit. The overvoltage protection circuit detects overvoltage events at a pad of the integrated circuit. The overvoltage protection circuit generates a max voltage signal that is the greater of the voltage at the pad and a supply voltage of the integrated circuit. The overvoltage protection circuit disables a PMOS transistor coupled to the pad by supplying the max voltage signal to the gate of the PMOS transistor when an overvoltage event is present at the pad.
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175.发明授权公开(公告)号：US11562115B2
公开(公告)日：2023-01-24
申请号：US15423284
申请日：2017-02-02
Inventor： Thomas Boesch , Giuseppe Desoli
IPC: G06N3/04 , G06F30/327 , G06N20/10 , G06N3/08 , G06F30/34 , G06N20/00 , G06N7/00 , G06F115/08 , G06N3/063 , G06F9/445 , G06F13/40 , G06F15/78
Abstract: Embodiments are directed towards a configurable accelerator framework device that includes a stream switch and a plurality of convolution accelerators. The stream switch has a plurality of input ports and a plurality of output ports. Each of the input ports is configurable at run time to unidirectionally pass data to any one or more of the output ports via a stream link. Each one of the plurality of convolution accelerators is configurable at run time to unidirectionally receive input data via at least two of the plurality of stream switch output ports, and each one of the plurality of convolution accelerators is further configurable at run time to unidirectionally communicate output data via an input port of the stream switch.
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Patent Agency Ranking
公开(公告)号：US20230018738A1
公开(公告)日：2023-01-19
申请号：US17812122
申请日：2022-07-12
Inventor： Francesco La Rosa , Marco Bildgen
IPC: G11C16/04 , H01L27/11524 , G11C16/08 , G11C16/10 , G11C16/26
Abstract: In an embodiment a noon-volatile memory device includes a memory plane including at least one memory area including an array of memory cells having two rows and N columns, wherein each memory cell comprises a state transistor having a control gate and a floating gate selectable by a vertical selection transistor buried in a substrate and including a buried selection gate, and wherein each column of memory cells includes a pair of twin memory cells, two selection transistors of the pair of twin memory cells having a common selection gate and a processor configured to store in the memory area information including a succession of N bits so that, with exception of the last bit of the succession, a current bit of the succession is stored in two memory cells located on the same row and on two adjacent columns and a current bit and the following bit are respectively stored in two twin cells.
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公开(公告)号：US20230015002A1
公开(公告)日：2023-01-19
申请号：US17852677
申请日：2022-06-29
Applicant: STMicroelectronics International N.V.
Inventor： Harsh RAWAT , Praveen Kumar VERMA
IPC: G11C11/419 , G11C11/412
Abstract: A method of memory reset includes precharging bit lines of a memory array, asserting a signal at a reset node to remove the precharge voltage, and selecting write drivers associated with the bit lines associated with columns of the memory array that contain memory cells to be reset, with the assertion of the signal at the reset node also resulting in application of desired logic states to inputs of the selected write drivers to cause those selected write drivers to change a logic state of the bit lines associated with those write drivers. The method continues with asserting each word line associated with a row of the memory that contains memory cells to be reset to write desired logic states to all of the memory cells of the columns and rows of the memory to be reset during a single clock cycle, and then deasserting those word lines.
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公开(公告)号：US11552646B2
公开(公告)日：2023-01-10
申请号：US17354126
申请日：2021-06-22
Applicant: STMicroelectronics International N.V.
Inventor： Ankur Bal , Vikram Singh
Abstract: A time-interleaved analog to digital converter (TI-ADC) includes a first sub-ADC configured to sample and convert an input analog signal to generate a first digital signal and a second sub-ADC configured to sample and convert said input analog signal to generate a second digital signal. Sampling by the second sub-ADC occurs with a time skew mismatch. A multiplexor interleaves the first and second digital signals to generate a third digital signal. A time skew mismatch error determination circuit processes the first and second digital signals to generate a time error corresponding to the time skew mismatch. A slope value of said third digital signal is determined and multiplied by the time error to generate a signal error. The signal error is summed with the third digital signal to generate a digital output signal which eliminates the error due to the time skew mismatch. This correction is performed in real time.
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公开(公告)号：US11550749B2
公开(公告)日：2023-01-10
申请号：US17143679
申请日：2021-01-07
Inventor： Manoj Kumar , Kailash Kumar , Nicolas Demange
Abstract: A serial peripheral interface (SPI) device includes a serial clock (SCK) pad receiving a serial clock, first and second Schmitt triggers directly electrically connected to the SCK pad to selectively respectively generate first and second clocks in response to rising and falling edges of the serial clock, first and second flip flops clocked by the first and second clocks to output bits of data to a data node, a multiplexer having an input coupled to the data node and an output coupled to driving circuitry, and driving circuitry transmitting data via a master-in-slave-out (MISO) pad.
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公开(公告)号：US11550531B2
公开(公告)日：2023-01-10
申请号：US17380754
申请日：2021-07-20
Inventor： Benedetto Vigna , Mahesh Chowdhary , Matteo Dameno
Abstract: A method includes receiving, at a master agent, announcements from candidate consumer agents indicating the presence of the candidate consumer agents. Each announcement includes display parameters for a display of the corresponding candidate consumer agent. The method further includes receiving at the master agent content parameters from a producer agent, the content parameters defining characteristics of content to be provided by the consumer agent. A mosaic screen is configured based on the received announcements and the content parameters. This configuring of the mosaic screen includes selecting ones of the consumer agents for which an announcement was received and generating content distribution parameters based on the content parameters and the display parameters of the selected ones of the consumer agents. The generated content distribution parameters are provided to the consumer agent.
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