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公开(公告)号：US20230245699A1
公开(公告)日：2023-08-03
申请号：US18148380
申请日：2022-12-29
Applicant: STMICROELECTRONICS S.r.l.
IPC: G11C13/00
CPC classification number: G11C13/004 , G11C13/0004 , G11C2013/0045 , G11C2013/0054
Abstract: The present disclosure is directed to a sense amplifier architecture for a memory device having a plurality of memory cells. Groups of non-volatile memory cells store respective codewords formed by stored logic states, logic high or logic low, of the memory cells of the group. The sense amplifier architecture has a plurality of sense amplifier reading branches, each sense amplifier reading branch coupled to a respective memory cell and configured to provide an output signal, which is indicative of a cell current flowing through the same memory cell; a comparison stage, to perform a comparison between the cell currents of memory cells of a group; and a logic stage, to determine, based on comparison results provided by the comparison stage, a read codeword corresponding to the group of memory cells. Information may be stored in different subsets of codewords, the sense amplifier architecture in this case having a subset definition circuit, to allow a preliminary determination of the subset to which a codeword to be read belongs to, based on reference signals.
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公开(公告)号：US20230243886A1
公开(公告)日：2023-08-03
申请号：US17592171
申请日：2022-02-03
Applicant: STMicroelectronics S.r.l.
Inventor： Filippo Colombo
IPC: G01R31/316 , G01R31/317
CPC classification number: G01R31/316 , G01R31/31704
Abstract: An integrated circuit (IC) includes: a first functional analog pin or pad; a first analog test bus coupled to the first functional analog pin or pad; first and second analog circuits coupled to the first analog test bus; and a test controller configured to: when the IC is in a functional operating mode, connect an input or output of the first analog circuit to the first analog test bus so that the input or output of the first analog circuit is accessible by the first functional analog pin or pad, and keep disconnected an input or output of the second analog circuit from the first analog test bus, and when the IC is in a test mode, selectively connect the input or output of the first and second analog circuits to the first analog test bus to test the first and second analog circuits using the first analog test bus.
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公开(公告)号：US11716061B2
公开(公告)日：2023-08-01
申请号：US17665399
申请日：2022-02-04
Applicant: STMicroelectronics S.r.l.
Inventor： Roberto Modaffari , Germano Nicollini
CPC classification number: H03F3/45273 , H03F3/45269 , H03F2203/45526
Abstract: A circuit for startup of a multi-stage amplifier circuit includes a pair of input nodes and at least two output nodes configured to be coupled to a multi-stage amplifier circuit. A startup differential stage includes a differential pair of transistors having respective control terminals coupled to the pair of input nodes, and each transistor in the differential pair of transistors has a respective current path therethrough between a respective output node and a common source terminal. The startup differential stage is configured to sense a common mode voltage drop at a first differential stage of the multi-stage amplifier circuit. Current mirror circuitry includes a plurality of transistors coupled to the common terminal of the differential pair of transistors and coupled to two output nodes of the at least two output nodes.
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公开(公告)号：US20230234836A1
公开(公告)日：2023-07-27
申请号：US17583896
申请日：2022-01-25
Applicant: STMicroelectronics S.r.l.
Inventor： Raffaele Enrico FURCERI , Luca MOLINARI
CPC classification number: B81B7/008 , B81B3/0043 , G02B26/0833 , B81B2201/042 , B81B2207/03
Abstract: Techniques to be described herein are based upon the combination of a digital lock-in amplifier approach with a numerical method to yield accurate estimations of the amplitude and phase of a sense signal obtained from a movement sensor associated with a resonant MEMS device such as a MEMS mirror. The techniques described herein are efficient from a computational point of view, in a manner which is suitable for applications in which the implementing hardware is to follow size and power consumption constraints.
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175.发明授权公开(公告)号：US11709185B2
公开(公告)日：2023-07-25
申请号：US17670858
申请日：2022-02-14
Applicant: STMicroelectronics S.r.l.
Inventor： Michele Vaiana , Calogero Marco Ippolito , Angelo Recchia , Antonio Cicero , Pierpaolo Lombardo
CPC classification number: G01R19/0038 , G01R19/0069 , G05F3/08 , H03B5/04 , H03F1/0205 , H03F3/4565
Abstract: An amplification interface includes first and second differential input terminals, first and second differential output terminals providing first and second output voltages defining a differential output signal, and first and second analog integrators coupled between the first and second differential input terminals and the first and second differential output terminals, the first and second analog integrators being resettable by a reset signal. A control circuit generates the reset signal such that the first and second analog integrators are periodically reset during a reset interval and activated during a measurement interval, receives a control signal indicative of offsets in the measurement sensor current and the reference sensor current, and generates a drive signal as a function of the control signal. First and second current generators coupled first and second compensation circuits to the first and second differential input terminals as a function of a drive signal.
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Patent Agency Ranking
176.发明公开公开(公告)号：US20230215819A1
公开(公告)日：2023-07-06
申请号：US18121145
申请日：2023-03-14
Applicant: STMicroelectronics S.r.l.
Inventor： Paolo CREMA
IPC: B23K26/354 , H01L23/495 , B23K26/0622
CPC classification number: B23K26/354 , H01L23/49582 , H01L23/49503 , B23K26/0622 , B23K2103/08
Abstract: A leadframe has a die pad area and an outer layer of a first metal having a first oxidation potential. The leadframe is placed in contact with a solution containing a second metal having a second oxidation potential, the second oxidation potential being more negative than the first oxidation potential. Radiation energy is then applied to the die pad area of the leadframe contacted with the solution to cause a local increase in temperature of the leadframe. As a result of the temperature increase, a layer of said second metal is selectively provided at the die pad area of the leadframe by a galvanic displacement reaction. An oxidation of the outer layer of the leadframe is then performed to provide an enhancing layer which counters device package delamination.
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177.发明公开公开(公告)号：US20230210435A1
公开(公告)日：2023-07-06
申请号：US18146259
申请日：2022-12-23
Applicant: STMICROELECTRONICS S.r.l.
Inventor： Alessandro GUMIERO , Luigi DELLA TORRE
CPC classification number: A61B5/332 , A61B5/0006 , A61B5/6823
Abstract: The present disclosure is directed to a solid body for a biomedical device, wearable by a patient and configured to acquire one or more physiological parameters of the patient. The solid body includes a first rigid portion, a second rigid portion and a connection portion of flexible type which couples the first and the second rigid portions to each other; and a control circuitry accommodated inside the first and/or the second rigid portions. The connection portion is interposed between the first and the second rigid portions, is integral therewith and is deformable so as to allow a relative movement of the first and the second rigid portions. The first and the second rigid portions are physically couplable to a first and to a second ECG electrode to couple the solid body to the torso of the patient. When the rigid portions are coupled to the ECG electrodes, the control circuitry is electrically coupled to the ECG electrodes and is configured to acquire, through the ECG electrodes, respective electrical signals indicative of said one or more physiological parameters.
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公开(公告)号：US11696507B2
公开(公告)日：2023-07-04
申请号：US16706567
申请日：2019-12-06
Applicant: STMICROELECTRONICS S.R.L.
Inventor： Domenico Giusti , Carlo Luigi Prelini
CPC classification number: H10N30/2042 , B81B3/0018 , B81B3/0072 , B81B2201/032
Abstract: A MEMS device having a body with a first and a second surface, a first portion and a second portion. The MEMS device further has a cavity extending in the body from the second surface; a deformable portion between the first surface and the cavity; and a piezoelectric actuator arranged on the first surface, on the deformable portion. The deformable portion has a first region with a first thickness and a second region with a second thickness greater than the first thickness. The second region is adjacent to the first region and to the first portion of the body.
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公开(公告)号：US11696504B2
公开(公告)日：2023-07-04
申请号：US17321252
申请日：2021-05-14
Applicant: STMICROELECTRONICS S.r.l.
Inventor： Paolo Ferrari , Flavio Francesco Villa , Lucia Zullino , Andrea Nomellini , Luca Seghizzi , Luca Zanotti , Bruno Murari , Martina Scolari
IPC: H10N10/855 , H10N10/01 , H10N10/17
CPC classification number: H10N10/855 , H10N10/01 , H10N10/17
Abstract: A method of fabricating a thermoelectric converter that includes providing a layer of a Silicon-based material having a first surface and a second surface, opposite to and separated from the first surface by a Silicon-based material layer thickness; forming a plurality of first thermoelectrically active elements of a first thermoelectric semiconductor material having a first Seebeck coefficient, and forming a plurality of second thermoelectrically active elements of a second thermoelectric semiconductor material having a second Seebeck coefficient, wherein the first and second thermoelectrically active elements are formed to extend through the Silicon-based material layer thickness, from the first surface to the second surface; forming electrically conductive interconnections in correspondence of the first surface and of the second surface of the layer of Silicon-based material, for electrically interconnecting the plurality of first thermoelectrically active elements and the plurality of second thermoelectrically active elements, and forming an input electrical terminal and an output electrical terminal electrically connected to the electrically conductive interconnections, wherein the first thermoelectric semiconductor material and the second thermoelectric semiconductor material comprise Silicon-based materials selected among porous Silicon or polycrystalline SiGe or polycrystalline Silicon.
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公开(公告)号：US11696072B2
公开(公告)日：2023-07-04
申请号：US17517273
申请日：2021-11-02
Applicant: STMicroelectronics S.r.l.
Inventor： Marco Passoni
Abstract: An electro-acoustical transducer such as a Piezoelectric Micromachined Ultrasonic Transducers is coupled with an adjustable load circuit having a set of adjustable load parameters including resistance and inductance parameters. Starting from at least one resonance frequency or at least one ring-down parameter of the electro-acoustical transducer a set of model parameters is calculated for a Butterworth-Van Dyke (BVD) model of the electro-acoustical transducer. The BVD model includes an equivalent circuit network having a constant capacitance coupled to a RLC branch and the adjustable load circuit is coupled with the electro-acoustical transducer at an input port of the equivalent circuit network of the model of the electro-acoustical transducer. The adjustable load parameters are adjusted as a function of the set of model parameters calculated for the BVD model of the electro-acoustic transducer to increase the bandwidth or the sensitivity of the electro-acoustic transducer.
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