公开(公告)号：US11917836B2

公开(公告)日：2024-02-27

申请号：US17513851

申请日：2021-10-28

Applicant: United Microelectronics Corp.

Inventor： Zong-Han Lin

IPC: H10N70/00 ,  H10B63/00

CPC classification number: H10B63/30 ,  H10N70/841 ,  H10N70/8833

Abstract: The invention provides a RRAM structure, which includes a substrate, a high voltage transistor, and a RRAM cell. The high voltage transistor includes a drift region, a gate structure, a source region, a drain region, and an isolation structure. The drift region is located in the substrate. The gate structure is located on the substrate and on a portion of the drift region. The source region and the drain region are located in the substrate on two sides of the gate structure. The drain region is located in the drift region. The isolation structure is located in the drift region and between the gate structure and the drain region. The RRAM cell includes a first electrode, a resistive switching layer, and a second electrode sequentially located on the drain region. The RRAM cell is electrically connected to the high voltage transistor.

公开(公告)号：US11916075B2

公开(公告)日：2024-02-27

申请号：US17741123

申请日：2022-05-10

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Wei-Lun Hsu ,  Yung-Chien Kung ,  Ming-Tsung Yeh ,  Yan-Hsiu Liu ,  Am-Tay Luy ,  Yao-Pi Hsu ,  Ji-Fu Kung

IPC: H01L29/423 ,  H01L27/092 ,  H01L21/762 ,  H01L21/8238 ,  H01L21/761 ,  H01L21/8234 ,  H01L29/78

CPC classification number: H01L27/0922 ,  H01L21/761 ,  H01L21/76224 ,  H01L21/823878 ,  H01L21/823481 ,  H01L21/823892 ,  H01L29/7813

Abstract: An integrated circuit (IC) structure includes a substrate having several regions, several semiconductor devices formed at the substrate and respectively within the regions, and an ultra-deep (UD) trench isolation structure formed in the substrate. The substrate has a top surface and a bottom surface oppositely, and the UD trench isolation structure formed in the substrate surrounds peripheries of each of the regions for structurally and physically isolating the semiconductor devices within different regions. The UD trench isolation structure penetrates the substrate by extending from the top surface of the substrate to the bottom surface of the substrate.

公开(公告)号：US20240063774A1

公开(公告)日：2024-02-22

申请号：US18499222

申请日：2023-11-01

Applicant: United Microelectronics Corp.

Inventor： Chen-Hsiao Wang ,  Kai-Kuang Ho

IPC: H03H9/10 ,  H03H3/08 ,  H03H9/25 ,  H03H9/02 ,  H10N30/02 ,  H10N30/88

CPC classification number: H03H9/1092 ,  H03H3/08 ,  H03H9/25 ,  H03H9/02937 ,  H10N30/02 ,  H10N30/883 ,  Y10T29/49005 ,  Y10T29/42

Abstract: A surface acoustic wave (SAW) device including a substrate is provided. Multiple surface acoustic wave elements are disposed on the substrate. A conductive surrounding structure includes: a wall part, disposed on the substrate and surrounding the surface acoustic wave elements; and a lateral layer part, disposed on the wall part. The lateral layer part has an opening above the surface acoustic wave elements. A cap layer covers the lateral layer part and closes the opening.

公开(公告)号：US20240057488A1

公开(公告)日：2024-02-15

申请号：US18382055

申请日：2023-10-19

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chia-Ching Hsu ,  Wang Xiang ,  Shen-De Wang

IPC: H10N70/00 ,  H10B63/00

CPC classification number: H10N70/841 ,  H10B63/845 ,  H10N70/021 ,  H10N70/066 ,  H10N70/8833

Abstract: A RRAM (resistive random-access memory) device includes a bottom electrode line, a top electrode island and a resistive material. The bottom electrode line is directly on a first metal structure. The top electrode island is disposed beside the bottom electrode line. The resistive material is sandwiched by a sidewall of the bottom electrode line and a sidewall of the top electrode island. The present invention also provides a method of forming the RRAM device.

公开(公告)号：US20240047554A1

公开(公告)日：2024-02-08

申请号：US17899604

申请日：2022-08-30

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Zhi-Cheng Lee ,  Huai-Tzu Chiang ,  Chuang-Han Hsieh ,  Kai-Lin Lee

IPC: H01L29/66 ,  H01L29/778 ,  H01L23/31

CPC classification number: H01L29/66462 ,  H01L29/778 ,  H01L23/3171 ,  H01L23/3192 ,  H01L29/2003

Abstract: A manufacturing method of a semiconductor device includes the following steps. A III-V compound barrier layer is formed on a III-V compound semiconductor layer. A protection layer is formed on the III-V compound barrier layer. An opening is formed penetrating through the protection layer in a vertical direction and exposing a part of the III-V compound barrier layer. A p-type doped III-V compound material is formed in the opening. A patterned barrier layer is formed on the p-type doped III-V compound material. A contact area between the patterned barrier layer and the p-type doped III-V compound material is less than an area of a top surface of the p-type doped III-V compound material.

公开(公告)号：US11895848B2

公开(公告)日：2024-02-06

申请号：US17750386

申请日：2022-05-22

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ya-Huei Tsai ,  Rai-Min Huang ,  Yu-Ping Wang ,  Hung-Yueh Chen

IPC: H10B61/00 ,  H01L23/528 ,  H10N50/80 ,  G11C11/16 ,  H01F10/32 ,  H10N50/85

CPC classification number: H10B61/22 ,  H01L23/528 ,  H10N50/80 ,  G11C11/161 ,  H01F10/3254 ,  H10N50/85

Abstract: A layout pattern for magnetoresistive random access memory (MRAM) includes a substrate having a first active region, a second active region, and a word line connecting region between the first active region and the second active region, a first gate pattern extending along a first direction from the first active region to the second active region, a second gate pattern extending along the first direction from the first active region to the second active region, a first magnetic tunneling junction (MTJ) between the first gate pattern and the second pattern and within the word line connecting region, and a second MTJ between the first gate pattern and the second gate pattern in the first active region. Preferably, top surfaces of the first MTJ and the second MTJ are coplanar.

公开(公告)号：US11895847B2

公开(公告)日：2024-02-06

申请号：US17987795

申请日：2022-11-15

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ting-Hsiang Huang ,  Yi-Chung Sheng ,  Sheng-Yuan Hsueh ,  Kuo-Hsing Lee ,  Chih-Kai Kang

IPC: H10B61/00 ,  H10N50/10 ,  H10N50/80

CPC classification number: H10B61/10 ,  H10N50/10 ,  H10N50/80

Abstract: A semiconductor device includes a substrate having a magnetic tunneling junction (MTJ) region and a logic region, a magnetic tunneling junction (MTJ) on the MTJ region and a first metal interconnection on the MTJ. Preferably, a top view of the MTJ includes a circle and a top view of the first metal interconnection includes an ellipse overlapping the circle.

公开(公告)号：US20240032440A1

公开(公告)日：2024-01-25

申请号：US18376437

申请日：2023-10-03

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hui-Lin Wang ,  Chia-Chang Hsu ,  Chen-Yi Weng ,  Chin-Yang Hsieh ,  Jing-Yin Jhang

IPC: H10N50/80 ,  H01F41/34 ,  H01F10/32 ,  G11C11/16 ,  H10B61/00 ,  H10N50/01

CPC classification number: H10N50/80 ,  H01F41/34 ,  H01F10/3254 ,  G11C11/161 ,  H10B61/00 ,  H10N50/01 ,  H10N50/85

Abstract: A semiconductor device includes a substrate comprising a MTJ region and a logic region, a magnetic tunneling junction (MTJ) on the MTJ region, and a contact plug on the logic region. Preferably, the MTJ includes a bottom electrode layer having a gradient concentration, a free layer on the bottom electrode layer, and a top electrode layer on the free layer.

公开(公告)号：US11881529B2

公开(公告)日：2024-01-23

申请号：US17902928

申请日：2022-09-05

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Purakh Raj Verma ,  Ching-Yang Wen ,  Li Wang ,  Kai Cheng

IPC: H01L23/52 ,  H01L29/78 ,  H01L29/06 ,  H01L29/66 ,  H01L29/40 ,  H01L29/417

CPC classification number: H01L29/7838 ,  H01L29/0649 ,  H01L29/401 ,  H01L29/41725 ,  H01L29/66484 ,  H01L29/7831

Abstract: A method of fabricating a semiconductor device is provided. First, a semiconductor structure is provided, and the semiconductor structure includes a buried dielectric layer, a first gate structure disposed on a front-side of the buried dielectric layer, and a first source/drain region and a second source/drain region disposed between the buried dielectric layer and the first gate structure. Then, a trench is formed in the buried dielectric layer. Afterwards, a conductive layer is formed on the buried dielectric layer and in the trench. Finally, the conductive layer is patterned.

公开(公告)号：US20240021702A1

公开(公告)日：2024-01-18

申请号：US17885574

申请日：2022-08-11

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Zhi-Cheng Lee ,  Chuang-Han Hsieh ,  Huai-Tzu Chiang ,  Kai-Lin Lee

IPC: H01L29/66 ,  H01L29/20 ,  H01L29/778

CPC classification number: H01L29/66462 ,  H01L29/2003 ,  H01L29/7786

Abstract: An HEMT includes a first III-V compound layer, a second III-V compound layer, and a III-V compound cap layer. The second III-V compound layer is disposed on the first III-V compound layer. The III-V compound cap layer covers and contacts the second III-V compound layer. The composition of the III-V compound cap layer and the second III-V compound layer are different from each other. A first opening is disposed in the III-V compound cap layer. A first insulating layer includes two first insulating parts and two second insulating parts. The two first insulating parts cover a top surface of the III-V compound cap layer, and the two second insulating parts respectively contact two sidewalls of the first opening. A second opening is disposed between the two first insulating parts and between the two second insulating parts. A gate electrode is disposed in the second opening.