中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

212 records (took 0.061 seconds)

    USE OF BAND EDGE GATE METALS AS SOURCE DRAIN CONTACTS
    171.
    发明申请
    USE OF BAND EDGE GATE METALS AS SOURCE DRAIN CONTACTS 审中-公开
    使用带边缘金属作为源漏联系

    公开(公告)号：US20130241007A1

    公开(公告)日：2013-09-19

    申请号：US13421276

    申请日：2012-03-15

    Applicant: Kisik Choi ,  Christian Lavoie ,  Paul M. Solomon ,  Bin Yang ,  Zhen Zhang

    Inventor： Kisik Choi ,  Christian Lavoie ,  Paul M. Solomon ,  Bin Yang ,  Zhen Zhang

    IPC: H01L29/78 ,  H01L21/283

    CPC classification number: H01L29/7833 ,  H01L21/28512 ,  H01L29/4958 ,  H01L29/4966 ,  H01L29/66545

    Abstract: A method includes providing a semiconductor substrate having intentionally doped surface regions, the intentionally doped surface regions corresponding to locations of a source and a drain of a transistor; depositing a layer a band edge gate metal onto a gate insulator layer in a gate region of the transistor while simultaneously depositing the band edge gate metal onto the surface of the semiconductor substrate to be in contact with the intentionally doped surface regions; and depositing a layer of contact metal over the band edge gate metal in the gate region and in the locations of the source and the drain. The band edge gate metal in the source/drain regions reduces a Schottky barrier height of source/drain contacts of the transistor and serves to reduce contact resistance. A transistor fabricated in accordance with the method is also described.

    Abstract translation: 一种方法包括提供具有有意掺杂的表面区域的半导体衬底，有意掺杂的表面区域对应于晶体管的源极和漏极的位置; 在晶体管的栅极区域中的栅绝缘体层上沉积带边缘栅极金属层，同时将带边缘栅极金属沉积到半导体衬底的表面上以与有意掺杂的表面区域接触; 以及在所述栅极区域中以及所述源极和漏极的位置中的所述带边缘栅极金属之上沉积接触金属层。 源极/漏极区域中的带边缘栅极金属降低了晶体管的源极/漏极接触的肖特基势垒高度，并且用于降低接触电阻。 还描述了根据该方法制造的晶体管。

    Image processing method and apparatus
    174.
    发明授权
    Image processing method and apparatus 失效
    图像处理方法和装置

    公开(公告)号：US08462390B2

    公开(公告)日：2013-06-11

    申请号：US13124708

    申请日：2009-10-19

    Applicant: Haifeng Li ,  Shixiong Ma ,  Bin Yang ,  Lidong Wang

    Inventor： Haifeng Li ,  Shixiong Ma ,  Bin Yang ,  Lidong Wang

    IPC: H04N1/52

    CPC classification number: H04N1/52

    Abstract: An image processing method includes: generating a stochastic screening dither matrix (S101); performing a centered positive-negative conversion operation on the stochastic screening dither matrix (S102); generating a screen dot dither contrast matrix for each color surface according to the stochastic screening dither matrix after being subjected to the positive-negative conversion operation and a stochastic screening dither threshold set for each color surface of an image; performing a logical “and” operation between each data item in a one-bit amplitude modulation screen dot matrix of each color surface of the image and a data item at a corresponding position in the screen dot dither contrast matrix of the color surface, and using a result as a processed value of a corresponding data item in the one-bit amplitude modulation screen dot matrix of the color surface. An apparatus corresponding to the image processing method is also provided. According to the above-described image processing method and apparatus, the problem in the prior art of an excess of pure-color pixels existing in an original one-bit dot matrix can be resolved.

    Abstract translation: 一种图像处理方法包括：产生随机筛选抖动矩阵（S101）; 对随机筛选抖动矩阵执行中心正负转换操作（S102）; 根据随机筛选抖动矩阵在进行正负转换操作之后产生每个颜色表面的屏幕点抖动对比度矩阵，以及为图像的每个颜色表面设置的随机屏蔽抖动阈值; 在图像的每个颜色表面的一位幅度调制屏幕点阵中的每个数据项之间执行逻辑“和”操作，以及在颜色表面的屏幕点抖动对比矩阵中的相应位置处的数据项，并且使用 作为颜色表面的一位幅度调制屏幕点阵中的相应数据项的处理值的结果。 还提供了与图像处理方法对应的装置。 根据上述图像处理方法和装置，可以解决现有技术中存在于原始一位点阵中的纯色像素的过剩问题。

    Short channel semiconductor devices with reduced halo diffusion
    175.
    发明授权
    Short channel semiconductor devices with reduced halo diffusion 有权
    具有减少晕圈扩散的短沟道半导体器件

    公开(公告)号：US08445342B2

    公开(公告)日：2013-05-21

    申请号：US12821507

    申请日：2010-06-23

    Applicant: Bin Yang ,  Man Fai Ng

    Inventor： Bin Yang ,  Man Fai Ng

    IPC: H01L21/338

    CPC classification number: H01L29/7816 ,  H01L21/823807 ,  H01L21/823828 ,  H01L27/092 ,  H01L29/66492 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66575 ,  H01L29/7833

    Abstract: A short channel semiconductor device is formed with halo regions that are separated from the bottom of the gate electrode and from each other. Embodiments include implanting halo regions after forming source/drain regions and source/drain extension regions. An embodiment includes forming source/drain extension regions in a substrate, forming source/drain regions in the substrate, forming halo regions under the source/drain extension regions, after forming the source drain regions, and forming a gate electrode on the substrate between the source/drain regions. By forming the halo regions after the high temperature processing involved informing the source/drain and source/drain extension regions, halo diffusion is minimized, thereby maintaining sufficient distance between halo regions and reducing short channel NMOS Vt roll-off.

    Abstract translation: 短沟道半导体器件形成有与栅电极的底部彼此分离的晕圈。 实施例包括在形成源极/漏极区域和源极/漏极延伸区域之后注入晕圈。 一个实施例包括在衬底中形成源极/漏极延伸区域，在衬底中形成源极/漏极区域，在形成源极漏极区域之后在源极/漏极延伸区域下方形成卤素区域，以及在衬底上形成栅极电极 源/漏区。 通过在涉及源极/漏极和源极/漏极延伸区域的高温处理之后形成晕圈区域，使得光晕扩散最小化，从而在晕圈区域之间保持足够的距离并且减少短沟道NMOS Vt滚降。

    USE OF EPITAXIAL NI SILICIDE
    178.
    发明申请
    USE OF EPITAXIAL NI SILICIDE 有权
    外用矽硅胶的使用

    公开(公告)号：US20130012020A1

    公开(公告)日：2013-01-10

    申请号：US13612240

    申请日：2012-09-12

    Applicant: Marwan H. Khater ,  Christian Lavoie ,  Bin Yang ,  Zhen Zhang

    Inventor： Marwan H. Khater ,  Christian Lavoie ,  Bin Yang ,  Zhen Zhang

    IPC: H01L21/3205

    CPC classification number: H01L29/7839 ,  H01L21/28052 ,  H01L21/28537 ,  H01L29/47 ,  H01L29/665 ,  H01L29/66643 ,  H01L29/66772 ,  H01L29/78618

    Abstract: An epitaxial Ni silicide film that is substantially non-agglomerated at high temperatures, and a method for forming the epitaxial Ni silicide film, is provided. The Ni silicide film of the present disclosure is especially useful in the formation of ETSOI (extremely thin silicon-on-insulator) Schottky junction source/drain FETs. The resulting epitaxial Ni silicide film exhibits improved thermal stability and does not agglomerate at high temperatures.

    Abstract translation: 提供了在高温下基本上未附聚的外延Ni硅化物膜，以及形成外延Ni硅化物膜的方法。 本公开的Ni硅化物膜特别可用于形成ETSOI（极薄的绝缘体上硅）肖特基结源极/漏极FET。 得到的外延Ni硅化物膜具有改善的热稳定性，并且在高温下不聚结。

    METAL GATE FILL BY OPTIMIZING ETCH IN SACRIFICIAL GATE PROFILE
    179.
    发明申请
    METAL GATE FILL BY OPTIMIZING ETCH IN SACRIFICIAL GATE PROFILE 有权
    金属门盖通过优化浇口配置文件进行优化

    公开(公告)号：US20130005128A1

    公开(公告)日：2013-01-03

    申请号：US13606035

    申请日：2012-09-07

    Applicant: Man Fai NG ,  Bin Yang

    Inventor： Man Fai NG ,  Bin Yang

    IPC: H01L21/283

    CPC classification number: H01L21/28114 ,  H01L29/42376 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/7833

    Abstract: A high-k metal gate electrode is formed with reduced gate voids. An embodiment includes forming a replaceable gate electrode, for example of amorphous silicon, having a top surface and a bottom surface, the top surface being larger than the bottom surface, removing the replaceable gate electrode, forming a cavity having a top opening larger than a bottom opening, and filling the cavity with metal. The larger top surface may be formed by etching the bottom portion of the amorphous silicon at greater temperature than the top portion, or by doping the top and bottom portions of the amorphous silicon differently such that the bottom has a greater lateral etch rate than the top.

    Abstract translation: 形成具有减小的栅极空隙的高k金属栅电极。 一个实施例包括形成可替换的栅电极，例如具有顶表面和底表面的非晶硅，顶表面大于底表面，去除可更换的栅电极，形成具有大于 底部开口，并用金属填充空腔。 可以通过在比顶部更高的温度下蚀刻非晶硅的底部，或者通过不同地掺杂非晶硅的顶部和底部来形成较大的顶表面，使得底部具有比顶部更大的横向蚀刻速率 。

Patent Agency Ranking