公开(公告)号：US10685949B2

公开(公告)日：2020-06-16

申请号：US15450900

申请日：2017-03-06

Applicant: Intel Corporation

Inventor： Aleksandar Aleksov ,  Mauro Kobrinsky ,  Johanna Swan ,  Rajendra C. Dias

IPC: H01L25/00 ,  H05K1/14 ,  H01L23/00 ,  H05K1/02 ,  H05K1/03 ,  H05K1/11 ,  H05K3/46

Abstract: Generally discussed herein are systems and apparatuses that can include apparatuses, systems, or method for a flexible, wire bonded device. According to an example an apparatus can include (1) a first rigid circuit comprising a first plurality of bond pads proximate to a first edge of the first rigid circuit, (2) a second rigid circuit comprising a second plurality of bond pads proximate to a first edge of the second rigid circuit, the second rigid circuit adjacent the first rigid circuit and the first edge of the second rigid circuit facing the first edge of the first rigid circuit, or (3) a first plurality of wire bonded wires, each wire bonded wire of the first plurality of wire bonded wires electrically and mechanically connected to a bond pad of the first plurality of bond pads and a bond pad of the second plurality of bond pads.

公开(公告)号：US20200006235A1

公开(公告)日：2020-01-02

申请号：US16020295

申请日：2018-06-27

Applicant: Intel Corporation

Inventor： Aleksandar Aleksov ,  Johanna M. Swan

IPC: H01L23/538 ,  H01L25/18 ,  H01L23/13 ,  H01L25/00 ,  H01L21/48 ,  H01L23/66

Abstract: Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include a package substrate having a high bandwidth interconnect, a first interposer having high bandwidth circuitry coupled to the package substrate, wherein the high bandwidth circuitry of the first interposer is electrically coupled to the high bandwidth interconnect, and a second interposer having high bandwidth circuitry coupled to the package substrate, wherein the high bandwidth circuitry of the second interposer is electrically coupled to the high bandwidth interconnect, and wherein the first interposer is electrically coupled to the second interposer via the high bandwidth interconnect.

公开(公告)号：US10468357B2

公开(公告)日：2019-11-05

申请号：US15546958

申请日：2015-03-11

Applicant: Intel Corporation

Inventor： Rajendra C. Dias ,  Tatyana N. Andryushchenko ,  Mauro J. Kobrinsky ,  Aleksandar Aleksov ,  David W. Staines

IPC: H01L23/498 ,  H01L23/00 ,  H01L23/16 ,  H01L21/48 ,  H01L21/56 ,  H01L23/31

Abstract: Embodiments of the invention include a microelectronic device and methods for forming a microelectronic device. In an embodiment, the microelectronic device includes a semiconductor die that has one or more die contacts that are each electrically coupled to a contact pad by a conductive trace. The semiconductor die may have a first elastic modulus. The microelectronic device may also include an encapsulation layer over the semiconductor die and the conductive trace. The encapsulation layer may have a second elastic modulus that is less than the first elastic modulus. The microelectronic device may also include a first strain redistribution layer within the encapsulation layer. The first strain redistribution layer may have a footprint that covers the semiconductor die and a portion of the conductive traces. The strain redistribution layer may have a third elastic modulus that is less than the first elastic modulus and greater than the second elastic modulus.

公开(公告)号：US10453812B2

公开(公告)日：2019-10-22

申请号：US15855961

申请日：2017-12-27

Applicant: Intel Corporation

Inventor： Hiroki Tanaka ,  Aleksandar Aleksov ,  Sri Ranga Sai Boyapati ,  Robert A. May ,  Kristof Darmawikarta

IPC: H01L23/00 ,  H01L23/485 ,  H01L21/027

Abstract: Techniques that can assist with fabricating a semiconductor package that includes a zero misalignment-via (ZMV) and/or a trace formed using a polarization process are described. The disclosed techniques can result in creation of ZMVs and/or traces between the ZMVs using a process comprising application of polarized light to one or more resist layers (e.g., a photoresist layer, etc.). One embodiment of a technique includes modulating an intensity of light applied to one or more resist layers by interaction of a light source with a photomask and at least one polarizer such that one or more patterns are created on the one or more resist layers. One embodiment of another technique includes creating patterns on one or more resist layers with different types of polarized light formed from a photomask and at least one polarizer. The disclosed techniques can assist with reducing manufacturing costs, reducing development time, and increasing I/O density.

公开(公告)号：US10403564B2

公开(公告)日：2019-09-03

申请号：US15859332

申请日：2017-12-30

Applicant: Intel Corporation

Inventor： Aleksandar Aleksov ,  Hiroki Tanaka ,  Robert A. May ,  Kristof Darmawikarta ,  Changhua Liu ,  Chung Kwang Tan ,  Srinivas Pietambaram ,  Sri Ranga Sai Boyapati

IPC: H01L21/027 ,  H01L21/48 ,  H01L23/485 ,  H01L23/498 ,  H01L23/00

Abstract: Techniques that can assist with fabricating a package layer that includes a plurality of dual-damascene zero-misalignment-vias (dual-damascene ZMVs) and a trace between the dual-damascene ZMVs are described. The disclosed techniques allow for the dual-damascene ZMVs and their corresponding trace to be plated simultaneously in a single step or operation. As such, there is little or no misalignment between the dual-damascene ZMVs, the trace, and the metal pads connected to the ZMVs. In this way, one or more of the embodiments described herein can assist with reducing manufacturing costs, reducing development time of fabricating a package layer, and with increasing the I/O density in a semiconductor package.

公开(公告)号：US10381291B2

公开(公告)日：2019-08-13

申请号：US15745701

申请日：2015-09-25

Applicant: Intel Corporation

Inventor： Adel A. Elsherbini ,  Henning Braunisch ,  Brandon M. Rawlings ,  Aleksandar Aleksov ,  Feras Eid ,  Javier Soto

IPC: H01L23/48 ,  H01L21/48 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532

Abstract: Embodiments of the invention include conductive vias and methods for forming the conductive vias. In one embodiment, a via pad is formed over a first dielectric layer and a photoresist layer is formed over the first dielectric layer and the via pad. Embodiments may then include patterning the photoresist layer to form a via opening over the via pad and depositing a conductive material into the via opening to form a via over the via pad. Embodiments may then includeremoving the photoresist layer and forming a second dielectric layer over the first dielectric layer, the via pad, and the via. For example a top surface of the second dielectric layer is formed above a top surface of the via in some embodiments. Embodiments may then include recessing the second dielectric layer to expose a top portion of the via.

公开(公告)号：US10368439B2

公开(公告)日：2019-07-30

申请号：US14778027

申请日：2014-12-26

Applicant: Intel Corporation

Inventor： Adel A. Elsherbini ,  Aleksandar Aleksov ,  Sasha N. Oster ,  Shawna M. Liff

IPC: H05K7/00 ,  H05K1/11 ,  H05K1/14 ,  H05K1/18 ,  H05K3/30 ,  H05K3/36 ,  H01L25/16 ,  H01L23/58 ,  H05K1/02

Abstract: An apparatus including a substrate including a first side and an opposite second side; at least one first circuit device on the first side of the substrate, at least one second device on the second side of the substrate; and a support on the second side of the substrate, the support including interconnections connected to the at least one first and second circuit device, the support having a thickness dimension operable to define a dimension from the substrate greater than a thickness dimension of the at least one second circuit device. A method including disposing at least one first circuit component on a first side of a substrate; disposing at least one second circuit component on a second side of the substrate; and coupling a support to the substrate, the substrate defining a dimension from the substrate greater than a thickness dimension of the at least one second circuit component.

公开(公告)号：US20190198467A1

公开(公告)日：2019-06-27

申请号：US15855961

申请日：2017-12-27

Applicant: Intel Corporation

Inventor： Hiroki Tanaka ,  Aleksandar Aleksov ,  Sri Ranga Sai Boyapati ,  Robert A. May ,  Kristof Darmawikarta

IPC: H01L23/00 ,  H01L23/485 ,  H01L21/027

Abstract: Techniques that can assist with fabricating a semiconductor package that includes a zero misalignment-via (ZMV) and/or a trace formed using a polarization process are described. The disclosed techniques can result in creation of ZMVs and/or traces between the ZMVs using a process comprising application of polarized light to one or more resist layers (e.g., a photoresist layer, etc.). One embodiment of a technique includes modulating an intensity of light applied to one or more resist layers by interaction of a light source with a photomask and at least one polarizer such that one or more patterns are created on the one or more resist layers. One embodiment of another technique includes creating patterns on one or more resist layers with different types of polarized light formed from a photomask and at least one polarizer. The disclosed techniques can assist with reducing manufacturing costs, reducing development time, and increasing I/O density.

公开(公告)号：US10256521B2

公开(公告)日：2019-04-09

申请号：US15280823

申请日：2016-09-29

Applicant: Intel Corporation

Inventor： Adel A. Elsherbini ,  Sasha N. Oster ,  Johanna M. Swan ,  Georgios C. Dogiamis ,  Shawna M. Liff ,  Aleksandar Aleksov ,  Telesphor Kamgaing

IPC: H01P5/10 ,  H01P11/00 ,  H01P5/107

Abstract: The systems and methods described herein provide a traveling wave launcher system physically and communicably coupled to a semiconductor package and to a waveguide. The traveling wave launcher system includes a slot-line signal converter and a tapered slot launcher. The slot-line signal converter may be formed integral with the semiconductor package and includes a balun structure that converts the microstrip signal to a slot-line signal. The tapered slot launcher is communicably coupled to the slot-line signal converter and includes a first plate and a second plate that form a slot. The tapered slot launcher converts the slot-line signal to a traveling wave signal that is propagated to the waveguide.

公开(公告)号：US20190096798A1

公开(公告)日：2019-03-28

申请号：US15718012

申请日：2017-09-28

Applicant: Intel Corporation

Inventor： Aleksandar Aleksov ,  Arnab Sarkar ,  Arghya Sain ,  Kristof Darmawikarta ,  Henning Braunisch ,  Prashant D. Parmar ,  Sujit Sharan ,  Johanna M. Swan ,  Feras Eid

IPC: H01L23/50 ,  H01L21/48 ,  H01L23/498

CPC classification number: H01L23/50 ,  G06F17/5068 ,  G06F17/5077 ,  G06F2217/40 ,  H01L21/4853 ,  H01L21/486 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/49866 ,  H01L23/5225 ,  H01L23/5226 ,  H01L23/5286 ,  H01L24/05 ,  H01L24/13 ,  H01L24/16 ,  H01L2224/0401 ,  H01L2224/05083 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05164 ,  H01L2224/13022 ,  H01L2224/131 ,  H01L2224/16145 ,  H01L2924/1434 ,  H01L2924/15311 ,  H01L2924/3011 ,  H01L2924/014 ,  H01L2924/00014

Abstract: Aspects of the embodiments are directed to an IC chip that includes a substrate comprising a first metal layer, a second metal layer, and a ground plane residing on the first metal layer. The second metal layer can include a first signal trace, the first signal trace electrically coupled to a first signal pad residing in the first metal layer by a first signal via. The second metal layer can include a second signal trace, the second signal trace electrically coupled to a second signal pad residing in the first metal layer by a second signal via. The substrate can also include a ground trace residing in the second metal layer between the first signal trace and the second signal trace, the ground trace electrically coupled to the ground plane by a ground via. The vias coupled to the traces can include self-aligned or zero-misaligned vias.