公开(公告)号：US11526649B2

公开(公告)日：2022-12-13

申请号：US17195133

申请日：2021-03-08

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Cheok-Kei Lei ,  Jerry Chang Jui Kao ,  Chi-Lin Liu ,  Hui-Zhong Zhuang ,  Zhe-Wei Jiang ,  Chien-Hsing Li

IPC: G06F30/00 ,  G06F30/398 ,  G06F30/392 ,  G06F30/394 ,  H01L27/02 ,  H01L23/522

Abstract: A method of making an integrated circuit includes operations to identify reverse signal nets of the circuit layout, determine the parasitic capacitance in conductive lines, and determine how to adjust an integrated circuit layout to reduce the parasitic capacitance of the conductive lines to the reverse signal net. The method further includes an operation to determine whether to move one of the conductive lines in the integrated circuit layout, an operation to determine whether to insert an isolation structure between the conductive lines of the reverse signal net having parasitic capacitance, and operations to adjust the layout by moving a conductive line.

公开(公告)号：US11494543B2

公开(公告)日：2022-11-08

申请号：US16883575

申请日：2020-05-26

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： Cheok-Kei Lei ,  Yu-Chi Li ,  Chia-Wei Tseng ,  Zhe-Wei Jiang ,  Chi-Lin Liu ,  Jerry Chang-Jui Kao ,  Jung-Chan Yang ,  Chi-Yu Lu ,  Hui-Zhong Zhuang

IPC: G06F30/392 ,  G06F30/394 ,  G06F30/398

Abstract: A layout method comprises selecting a first and a second layout devices in a layout of an integrated circuit. The second layout device abuts the first layout device at a boundary therebetween. The layout method also comprises disposing a first and a second conductive paths across the boundary, and respectively disposing a first and a second cut layers on the first and second conductive paths nearby the boundary. The layout method also comprises disconnecting the first layout device from the second layout device by cutting the first conductive path into two conductive portions according to a first position of the first cut layer and cutting the second conductive path into two conductive portions a second position of the second cut layer. The layout method also comprises moving the first cut layer to align with the second cut layer.

公开(公告)号：US11461528B2

公开(公告)日：2022-10-04

申请号：US16908288

申请日：2020-06-22

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Jung-Chan Yang ,  Ting-Wei Chiang ,  Jerry Chang-Jui Kao ,  Hui-Zhong Zhuang ,  Lee-Chung Lu ,  Li-Chun Tien ,  Meng-Hung Shen ,  Shang-Chih Hsieh ,  Chi-Yu Lu

IPC: G06F30/394 ,  H01L23/522 ,  H01L27/118 ,  H01L23/528 ,  H01L27/02

Abstract: An integrated circuit structure includes a first, a second and a third set of conductive structures and a first and a second set of vias. The first set of conductive structures extend in a first direction, and is located at a first level. The second set of conductive structures extends in a second direction, overlaps the first set of conductive structures, and is located at a second level. The first set of vias is between, and electrically couples the first and the second set of conductive structures. The third set of conductive structures extends in the first direction, overlaps the second set of conductive structures, covers a portion of the first set of conductive structures, and is located at a third level. The second set of vias is between, and electrically couples the second and the third set of conductive structures.

公开(公告)号：US20220302026A1

公开(公告)日：2022-09-22

申请号：US17835281

申请日：2022-06-08

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Guo-Huei Wu ,  Hui-Zhong Zhuang ,  Chih-Liang Chen ,  Cheng-Chi Chuang ,  Shang-Wen Chang ,  Yi-Hsun Chiu

IPC: H01L23/522 ,  H01L21/768 ,  H01L23/528

Abstract: A semiconductor device includes a first gate structure extending along a first lateral direction. The semiconductor device includes a first interconnect structure, disposed above the first gate structure, that extends along a second lateral direction perpendicular to the first lateral direction. The first interconnect structure includes a first portion and a second portion electrically isolated from each other by a first dielectric structure. The semiconductor device includes a second interconnect structure, disposed between the first gate structure and the first interconnect structure, that electrically couples the first gate structure to the first portion of the first interconnect structure. The second interconnect structure includes a recessed portion that is substantially aligned with the first gate structure and the dielectric structure along a vertical direction.

公开(公告)号：US11315874B2

公开(公告)日：2022-04-26

申请号：US17021051

申请日：2020-09-15

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Li-Chun Tien ,  Chih-Liang Chen ,  Hui-Zhong Zhuang ,  Shun Li Chen ,  Ting Yu Chen

IPC: H01L23/528 ,  H01L27/092 ,  H01L21/8238 ,  H01L23/522

Abstract: A cell on an integrated circuit is provided. The cell includes: a fin structure; an intermediate fin structure connection metal track disposed in an intermediate fin structure connection metal layer above the fin structure, the intermediate fin structure connection metal track being connected to the fin structure; and a first intermediate gate connection metal track disposed in an intermediate gate connection metal layer above the intermediate fin structure connection metal layer, the first intermediate gate connection metal track being connected to the intermediate fin structure connection metal track. A first power supply terminal is connected to the first intermediate gate connection metal track.

公开(公告)号：US11151297B2

公开(公告)日：2021-10-19

申请号：US17065086

申请日：2020-10-07

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Po-Chia Lai ,  Ming-Chang Kuo ,  Jerry Chang Jui Kao ,  Wei-Ling Chang ,  Wei-Ren Chen ,  Hui-Zhong Zhuang ,  Stefan Rusu ,  Lee-Chung Lu

IPC: G06F30/392 ,  G06F119/06

Abstract: A method includes positioning adjacent first through fourth active regions in a cell of an IC layout diagram, the first active region being a first type of an n-type or a p-type and corresponding to a first total number of fins, the second active region being a second type of the n-type or the p-type and corresponding to a second total number of fins, the third active region being the second type and corresponding to a third total number of fins, and the fourth active region being the first type and corresponding to a fourth total number of fins. Each of the first and second total numbers of fins is greater than each of the third and fourth total numbers of fins, and at least one of the positioning the first, second, third, or fourth active regions is performed by a processor.

公开(公告)号：US11138360B2

公开(公告)日：2021-10-05

申请号：US16662827

申请日：2019-10-24

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： Po-Hsiang Huang ,  Chin-Chou Liu ,  Sheng-Hsiung Chen ,  Fong-Yuan Chang ,  Hui-Zhong Zhuang ,  Meng-Hsueh Wang ,  Yi-Kan Cheng ,  Chun-Chen Chen

IPC: G06F30/392 ,  H01L23/528 ,  H01L23/522 ,  G06F30/394 ,  G06F30/398 ,  G06F119/18

Abstract: A method of generating a layout diagram including a first level of metallization (M_1st level) including: identifying, in the layout diagram, a filler cell and a first functional cell substantially abutting the filler cell; the first functional cell including first and second side boundaries, first wiring patterns in the M_1st level, and representing corresponding first conductors in the first functional cell region; and first and second groups of cut patterns overlying corresponding portions of the first wiring patterns and being substantially aligned with the corresponding first and second side boundaries; adjusting one or more locations of corresponding one or more selected cut patterns of the second group thereby correspondingly elongating one or more selected ones of the first wiring patterns so as to be corresponding first elongated wiring patterns which extend across the second boundary of the first functional cell into the filler cell.

公开(公告)号：US11126775B2

公开(公告)日：2021-09-21

申请号：US16836631

申请日：2020-03-31

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： Shih-Wei Peng ,  Guo-Huei Wu ,  Wei-Cheng Lin ,  Hui-Zhong Zhuang ,  Jiann-Tyng Tzeng

IPC: G06F30/392 ,  G03F7/20 ,  G03F1/36 ,  G06F30/398

Abstract: An IC device includes a gate structure including an isolation layer laterally adjacent to a gate electrode, a transistor including a first S/D structure, a second S/D structure, and a channel extending through the gate electrode, a third S/D structure overlying the first S/D structure, a fourth S/D structure overlying the second S/D structure, and a conductive structure overlying the isolation layer and configured to electrically connect the third S/D structure to the fourth S/D structure.

公开(公告)号：US11080461B2

公开(公告)日：2021-08-03

申请号：US17027023

申请日：2020-09-21

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： Kuang-Ching Chang ,  Ting-Wei Chiang ,  Hui-Zhong Zhuang ,  Jung-Chan Yang

IPC: G06F30/398 ,  G06F30/347 ,  G06F30/3947 ,  G06F30/3953 ,  G06F30/392 ,  H03K19/00 ,  H01L25/00 ,  G06F111/04 ,  H03K19/018 ,  H03K19/0175 ,  H03K19/0185 ,  H03K17/687 ,  H03K19/17736

Abstract: A system for preparing an integrated circuit device design includes a memory for storing a plurality of preliminary integrated circuit design files; a processor for retrieving a preliminary integrated circuit design file from the memory; locating vertical abutments between adjacent device cell designs, identifying internal metal cuts on the adjacent device cell designs; determining and evaluating a horizontal spacing between the internal metal cuts a spacing threshold; and if the threshold is note met, shifting one cell horizontally relative to the other cell design by a predetermined distance to define a modified device layout, repeating the determining, evaluating, and shifting operations until the spacing threshold is satisfied; and identifying a next vertical abutment between and repeating the identifying, determining, shifting operations until the spacing threshold has been satisfied for all vertical abutments.

公开(公告)号：US11037957B2

公开(公告)日：2021-06-15

申请号：US16884898

申请日：2020-05-27

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： Hsueh-Chih Chou ,  Chia Hao Tu ,  Sang Hoo Dhong ,  Lee-Chung Lu ,  Li-Chun Tien ,  Ting-Wei Chiang ,  Hui-Zhong Zhuang

IPC: H01L27/118 ,  H01L27/02

Abstract: A semiconductor structure is disclosed. The semiconductor structure includes: a first standard cell; and a second standard cell; wherein a cell width of the first standard cell along a first direction is substantially the same as a cell width of the second standard cell along the first direction, and a cell height of the first standard cell along a second direction perpendicular to the first direction is substantially greater than a cell height of the second standard cell along the second direction.