公开(公告)号：US20080292823A1

公开(公告)日：2008-11-27

申请号：US12095282

申请日：2006-11-28

Applicant: Moo Seok Lee ,  Kwang Jin Lee ,  Yong-Cheol Shin

Inventor： Moo Seok Lee ,  Kwang Jin Lee ,  Yong-Cheol Shin

IPC: B32B3/20

CPC classification number: B01D69/08 ,  B01D67/0011 ,  B01D69/087 ,  B01D69/12 ,  B01D2325/24 ,  B01D2325/40 ,  Y10T428/1352 ,  Y10T428/1362 ,  Y10T428/1369 ,  Y10T428/1393

Abstract: A braid-reinforced composite hollow fiber membrane is disclosed. The braid-reinforced composite hollow fiber membrane comprising a reinforcing material of a tubular braid and a polymer resinous thin film coated on the surface of the tubular braid according to the present invention is characterized in that: the tubular braid comprises multifilaments made of monofilaments having a crimp rate of 2 to 40%, and the peeling strength of the tubular braid and a polymer resinous thin film coated on the surface thereof is 1 to 10 MPa. In the composite hollow fiber membrane, the crimp rate of the monofilaments constituting the tubular braid of the reinforcing material is 2 to 40%, thus the surface area of the tubular braid contacted with the polymer resinous thin film is increased. Thus, the peeling strength of the tubular braid and the polymer resinous thin film coated on the surface thereof is excellent.

Abstract translation: 公开了一种编织增强复合中空纤维膜。 根据本发明的包括管状编织物的增强材料和涂覆在管状编织物的表面上的聚合物树脂薄膜的编织增强复合中空纤维膜的特征在于：管状编织物包括由单丝制成的复丝， 卷曲率为2〜40％，管状编织物的剥离强度和表面涂布的聚合物树脂薄膜为1〜10MPa。 在复合中空纤维膜中，构成加强材料的管状编织物的单丝的卷曲率为2〜40％，因此与聚合物树脂薄膜接触的管状编织物的表面积增加。 因此，管状编织物和涂布在其表面上的聚合物树脂薄膜的剥离强度优异。

公开(公告)号：US20080291715A1

公开(公告)日：2008-11-27

申请号：US12116295

申请日：2008-05-07

Applicant: Mu-Hui PARK ,  Kwang-Jin LEE ,  Du-Eung KIM ,  Hye-Jin KIM ,  Woo-Yeong CHO

Inventor： Mu-Hui PARK ,  Kwang-Jin LEE ,  Du-Eung KIM ,  Hye-Jin KIM ,  Woo-Yeong CHO

IPC: G11C11/00 ,  G11C7/00

CPC classification number: G11C13/0038 ,  G11C7/04 ,  G11C11/5678 ,  G11C13/0004 ,  G11C13/004 ,  G11C29/02 ,  G11C29/026 ,  G11C29/028

Abstract: A nonvolatile memory device includes a nonvolatile memory cell, a read circuit and a control bias generating circuit. The nonvolatile memory cell has a resistance level that changes depending on stored data. The read circuit reads the resistance level of the nonvolatile memory cell by receiving a control bias and supplying the nonvolatile memory cell a read bias based on the control bias. The control bias generating circuit receives an input bias, generates the control bias based on the input bias and supplies the control bias to the read circuit. A slope of the control bias to the input bias is less than 1.

Abstract translation: 非易失性存储器件包括非易失性存储单元，读取电路和控制偏置产生电路。 非易失性存储单元具有根据存储的数据而改变的电阻水平。 读取电路通过接收控制偏置来读取非易失性存储单元的电阻电平，并且基于控制偏压向非易失性存储单元提供读取偏置。 控制偏置产生电路接收输入偏置，基于输入偏置产生控制偏压，并将控制偏压提供给读取电路。 对输入偏置的控制偏置的斜率小于1。

公开(公告)号：US20080159017A1

公开(公告)日：2008-07-03

申请号：US11955562

申请日：2007-12-13

Applicant: Hye-Jin KIM ,  Kwang-Jin LEE ,  Woo-Yeong CHO ,  Mu-Hui PARK

Inventor： Hye-Jin KIM ,  Kwang-Jin LEE ,  Woo-Yeong CHO ,  Mu-Hui PARK

IPC: G11C5/14

CPC classification number: G11C13/004 ,  G11C5/147 ,  G11C11/56 ,  G11C11/5678 ,  G11C13/0004 ,  G11C13/0038 ,  G11C16/30 ,  G11C2013/0054 ,  G11C2213/72

Abstract: There are provided a bias voltage generator, a semiconductor memory device having the bias voltage generator, and a method for generating the bias voltage. The bias voltage generator which generates the bias voltage to control a sensing current supplied to a memory cell for sensing data is characterized in that the bias voltage is output in response to an input voltage being applied, so that a slope of the bias voltage to the input voltage is different in at least two sections divided corresponding to a level of the input voltage.

Abstract translation: 提供了偏置电压发生器，具有偏置电压发生器的半导体存储器件以及用于产生偏置电压的方法。 产生用于控制提供给存储单元的感测电流以感测数据的偏置电压的偏置电压发生器的特征在于，响应于所施加的输入电压而输出偏置电压，使得偏置电压的斜率 至少两个部分的输入电压不同，对应于输入电压的电平。

公开(公告)号：US20080080240A1

公开(公告)日：2008-04-03

申请号：US11902424

申请日：2007-09-21

Applicant: Kwang-Jin Lee ,  Won-Seok Lee ,  Choong-Keun Kwak

Inventor： Kwang-Jin Lee ,  Won-Seok Lee ,  Choong-Keun Kwak

IPC: G11C16/00

CPC classification number: H01L27/10802 ,  G11C7/00 ,  G11C7/10 ,  G11C7/1051 ,  G11C7/1057 ,  G11C7/1084 ,  G11C11/4063 ,  H01L21/84 ,  H01L27/10844 ,  H01L27/1203 ,  H01L29/7841

Abstract: A non volatile memory device and a memory system having the same are disclosed. The non volatile memory device may include a memory cell array having a plurality of non volatile memory cells, a DRAM interface for exchanging data, a command and an address with an external device, a controller for selecting one of the memory cells in response to the address and performing a control operation for one of outputting data of the selected memory cell to the external device in response to the command and storing data received from the external device, and a DRAM buffer memory. The DRAM buffer memory has dynamic memory cells, and each of the dynamic memory cells has one transistor with a floating body.

Abstract translation: 公开了一种非易失性存储器件和具有该非易失性存储器件的存储器系统。 非易失性存储器件可以包括具有多个非易失性存储器单元的存储器单元阵列，用于交换数据的DRAM接口，与外部设备的命令和地址，用于响应于所述存储器单元选择所述存储器单元中的一个的控制器 对所述存储器单元的数据的输出响应于所述命令并存储从所述外部设备接收的数据以及DRAM缓冲存储器，对所述存储单元的数据进行输出的地址和执行控制操作。 DRAM缓冲存储器具有动态存储单元，并且每个动态存储单元具有一个具有浮体的晶体管。

公开(公告)号：US07352616B2

公开(公告)日：2008-04-01

申请号：US11319602

申请日：2005-12-29

Applicant: Sang-beom Kang ,  Du-eung Kim ,  Hyung-rok Oh ,  Kwang-jin Lee

Inventor： Sang-beom Kang ,  Du-eung Kim ,  Hyung-rok Oh ,  Kwang-jin Lee

IPC: G11C11/00

CPC classification number: G11C5/145 ,  G11C8/08 ,  G11C11/5678 ,  G11C13/0004 ,  G11C13/0028 ,  G11C13/0038 ,  G11C13/0069 ,  G11C2013/009

Abstract: A phase change random access memory on aspect includes a memory cell array block including a plurality of phase change memory cells, a column decoder, a row decoder, a column selector, and a write driver. The memory further includes a write boosting unit having a plurality of internal charge pumps which boost a first voltage to generate a write driving voltage which drives the write driver, where the number of internal charge pumps that are activated during a write operation is varied according to a number of phase change memory cells which are selected during the write operation. The memory still further includes a column boosting unit which boosts the first voltage to generate a column driving voltage which drives the column decoder, and a row boosting unit which boosts the first voltage to generate a row driving voltage which drives the row decoder.

Abstract translation: 一方面的相变随机存取存储器包括包括多个相变存储器单元，列解码器，行解码器，列选择器和写驱动器的存储单元阵列块。 存储器还包括具有多个内部电荷泵的写入升压单元，该多个内部电荷泵升压第一电压以产生驱动写入驱动器的写入驱动电压，其中在写入操作期间被激活的内部电荷泵的数量根据 在写入操作期间选择的多个相变存储器单元。 存储器还包括列升压单元，其升高第一电压以产生驱动列解码器的列驱动电压;以及行升压单元，其升高第一电压以产生驱动行解码器的行驱动电压。

公开(公告)号：US20080068897A1

公开(公告)日：2008-03-20

申请号：US11850128

申请日：2007-09-05

Applicant: Kwang-jin LEE ,  Woo-yeong CHO ,  Hye-jin KIM

Inventor： Kwang-jin LEE ,  Woo-yeong CHO ,  Hye-jin KIM

IPC: G11C7/10

CPC classification number: G11C7/1045 ,  G11C7/1078 ,  G11C7/1084 ,  G11C7/109 ,  G11C7/22

Abstract: A semiconductor memory device comprises a memory cell array comprising memory cells of a first type. The memory cell array performs write and read operations in response to signals designed for the operation of a memory cell array comprising memory cells of a type other than the first type.

Abstract translation: 半导体存储器件包括包括第一类型存储单元的存储单元阵列。 存储单元阵列响应于设计用于包括除了第一类型之外的类型的存储器单元的存储单元阵列的操作的信号执行写入和读取操作。

公开(公告)号：US20080055971A1

公开(公告)日：2008-03-06

申请号：US11834845

申请日：2007-08-07

Applicant: Hye-jin KIM ,  Kwang-jin LEE ,  Du-eung KIM

Inventor： Hye-jin KIM ,  Kwang-jin LEE ,  Du-eung KIM

IPC: G11C11/00

CPC classification number: G11C13/0064 ,  G11C11/5678 ,  G11C13/0004 ,  G11C13/0069 ,  G11C2013/0092

Abstract: A method of operating a phase change random access memory (PRAM) device comprises performing a program operation to store data in selected PRAM cells of the device, wherein the program operation comprises a plurality of sequential program loops. The method further comprises suspending the program operation in the middle of the program operation, and after suspending the program operation, resuming the program operation in response to a resume command.

Abstract translation: 一种操作相变随机存取存储器（PRAM）装置的方法包括执行程序操作以将数据存储在所述装置的所选择的PRAM单元中，其中所述程序操作包括多个顺序程序循环。 该方法还包括在编程操作的中间暂停编程操作，并且在暂停编程操作之后，响应于恢复命令恢复程序操作。

公开(公告)号：US20070217253A1

公开(公告)日：2007-09-20

申请号：US11486100

申请日：2006-07-14

Applicant: Hye-jin Kim ,  Kwang-jin Lee ,  Sang-Beom Kang ,  Mu-hui Park

Inventor： Hye-jin Kim ,  Kwang-jin Lee ,  Sang-Beom Kang ,  Mu-hui Park

IPC: G11C11/00

CPC classification number: G11C8/12 ,  G11C11/5678 ,  G11C13/0004 ,  G11C13/0061 ,  G11C13/0069 ,  G11C2013/0078

Abstract: A method of performing a program-suspend-read operation in a PRAM device comprises programming a write block comprising N unit program blocks in response to a program operation request, and suspending the program operation after programming M unit program blocks, where M is less than N, in response to a read operation request. The method further comprises executing the requested read operation, and then resuming the programming of the write data block and programming (N−M) remaining unit program blocks.

Abstract translation: 一种在PRAM设备中执行程序挂起读取操作的方法包括响应于程序操作请求编程包含N个单元程序块的写入块，并且在对M个单元程序块进行编程之后暂停编程操作，其中M小于 N，响应于读取操作请求。 该方法还包括执行所请求的读取操作，然后恢复写入数据块和编程（N-M）剩余单元程序块的编程。

公开(公告)号：US20070097741A1

公开(公告)日：2007-05-03

申请号：US11319602

申请日：2005-12-29

Applicant: Sang-beom Kang ,  Du-eung Kim ,  Hyung-rok Oh ,  Kwang-jin Lee

Inventor： Sang-beom Kang ,  Du-eung Kim ,  Hyung-rok Oh ,  Kwang-jin Lee

IPC: G11C11/00

CPC classification number: G11C5/145 ,  G11C8/08 ,  G11C11/5678 ,  G11C13/0004 ,  G11C13/0028 ,  G11C13/0038 ,  G11C13/0069 ,  G11C2013/009

Abstract: A phase change random access memory on aspect includes a memory cell array block including a plurality of phase change memory cells, a column decoder, a row decoder, a column selector, and a write driver. The memory further includes a write boosting unit having a plurality of internal charge pumps which boost a first voltage to generate a write driving voltage which drives the write driver, where the number of internal charge pumps that are activated during a write operation is varied according to a number of phase change memory cells which are selected during the write operation. The memory still further includes a column boosting unit which boosts the first voltage to generate a column driving voltage which drives the column decoder, and a row boosting unit which boosts the first voltage to generate a row driving voltage which drives the row decoder.

Abstract translation: 一方面的相变随机存取存储器包括包括多个相变存储器单元，列解码器，行解码器，列选择器和写驱动器的存储单元阵列块。 存储器还包括具有多个内部电荷泵的写入升压单元，该多个内部电荷泵升压第一电压以产生驱动写入驱动器的写入驱动电压，其中在写入操作期间被激活的内部电荷泵的数量根据 在写入操作期间选择的多个相变存储器单元。 存储器还包括列升压单元，其升高第一电压以产生驱动列解码器的列驱动电压;以及行升压单元，其升高第一电压以产生驱动行解码器的行驱动电压。

公开(公告)号：US20050119393A1

公开(公告)日：2005-06-02

申请号：US10472593

申请日：2003-01-14

Applicant: Jeong-Heon Ahn ,  Chang-Sun Han ,  Yong-Hun Lee ,  Seon-Hee Han ,  Kwang-Jin Lee ,  Hyung-Jun Son

Inventor： Jeong-Heon Ahn ,  Chang-Sun Han ,  Yong-Hun Lee ,  Seon-Hee Han ,  Kwang-Jin Lee ,  Hyung-Jun Son

IPC: C08F265/06 ,  C08F285/00 ,  C08L27/06 ,  C08L51/00 ,  C08F2/16

CPC classification number: C08F285/00 ,  C08L27/06 ,  C08L51/003 ,  Y10S525/902 ,  C08F220/18 ,  C08L2666/24

Abstract: The invention relates to an acrylic impact modifier having a core-shell structure that provides an acrylic impact modifier composition comprising (a) a rubber core containing an alkyl acrylate polymer comprising at least two layers having different cross-linking densities, and (b) a shell containing an alkyl methacrylate polymer; to a process for the preparation of the acrylic impact modifier; and to a poly(vinyl chloride) composition comprising it. The acrylic impact modifier imparting excellent impact resistance was invented by employing multi-stage polymerization and at the same time by controlling the swelling index of rubber particles by changing the degree of cross-linking from stage to stage. And the poly(vinyl chloride) comprising the impact modifier of the present invention has good weatherability as well as excellent impact strength.

Abstract translation: 本发明涉及具有提供丙烯酸类抗冲改性剂组合物的核 - 壳结构的丙烯酸类抗冲改性剂，其包含（a）含有至少两层具有不同交联密度的丙烯酸烷基酯聚合物的橡胶芯，和（b） 壳含有甲基丙烯酸烷基酯聚合物; 涉及制备丙烯酸类抗冲改性剂的方法; 和包含它的聚（氯乙烯）组合物。 通过采用多级聚合法，发明了赋予耐冲击性优异的丙烯酸类抗冲击改性剂，同时通过改变交联程度从阶段到控制橡胶粒子的溶胀指数。 并且包含本发明的抗冲改性剂的聚（氯乙烯）具有良好的耐候性以及优异的冲击强度。