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    Non-volatile phase-change memory device and associated program-suspend-read operation
    1.
    发明申请
    Non-volatile phase-change memory device and associated program-suspend-read operation 有权
    非易失性相变存储器件和相关的程序挂起读操作

    公开(公告)号：US20070217253A1

    公开(公告)日：2007-09-20

    申请号：US11486100

    申请日：2006-07-14

    申请人： Hye-jin Kim ,  Kwang-jin Lee ,  Sang-Beom Kang ,  Mu-hui Park

    发明人： Hye-jin Kim ,  Kwang-jin Lee ,  Sang-Beom Kang ,  Mu-hui Park

    IPC分类号： G11C11/00

    CPC分类号： G11C8/12 ,  G11C11/5678 ,  G11C13/0004 ,  G11C13/0061 ,  G11C13/0069 ,  G11C2013/0078

    摘要： A method of performing a program-suspend-read operation in a PRAM device comprises programming a write block comprising N unit program blocks in response to a program operation request, and suspending the program operation after programming M unit program blocks, where M is less than N, in response to a read operation request. The method further comprises executing the requested read operation, and then resuming the programming of the write data block and programming (N−M) remaining unit program blocks.

    摘要翻译： 一种在PRAM设备中执行程序挂起读取操作的方法包括响应于程序操作请求编程包含N个单元程序块的写入块，并且在对M个单元程序块进行编程之后暂停编程操作，其中M小于 N，响应于读取操作请求。 该方法还包括执行所请求的读取操作，然后恢复写入数据块和编程（N-M）剩余单元程序块的编程。

    Non-volatile phase-change memory device and associated program-suspend-read operation
    2.
    发明授权
    Non-volatile phase-change memory device and associated program-suspend-read operation 有权
    非易失性相变存储器件和相关的程序挂起读操作

    公开(公告)号：US07349245B2

    公开(公告)日：2008-03-25

    申请号：US11486100

    申请日：2006-07-14

    申请人： Hye-jin Kim ,  Kwang-jin Lee ,  Sang-Beom Kang ,  Mu-hui Park

    发明人： Hye-jin Kim ,  Kwang-jin Lee ,  Sang-Beom Kang ,  Mu-hui Park

    IPC分类号： G11C11/00 ,  G11C11/14

    CPC分类号： G11C8/12 ,  G11C11/5678 ,  G11C13/0004 ,  G11C13/0061 ,  G11C13/0069 ,  G11C2013/0078

    摘要： A method of performing a program-suspend-read operation in a PRAM device comprises programming a write block comprising N unit program blocks in response to a program operation request, and suspending the program operation after programming M unit program blocks, where M is less than N, in response to a read operation request. The method further comprises executing the requested read operation, and then resuming the programming of the write data block and programming (N−M) remaining unit program blocks.

    摘要翻译： 一种在PRAM设备中执行程序挂起读取操作的方法包括响应于程序操作请求编程包含N个单元程序块的写入块，并且在对M个单元程序块进行编程之后暂停编程操作，其中M小于 N，响应于读取操作请求。 该方法还包括执行所请求的读取操作，然后恢复写入数据块和编程（N-M）剩余单元程序块的编程。

    Semiconductor memory device and method for reducing cell activation during write operations
    4.
    发明授权
    Semiconductor memory device and method for reducing cell activation during write operations 有权
    用于在写入操作期间减少电池激活的半导体存储器件和方法

    公开(公告)号：US07542356B2

    公开(公告)日：2009-06-02

    申请号：US11790146

    申请日：2007-04-24

    申请人： Kwang-Jin Lee ,  Sang-Beom Kang ,  Hyung-Rok Oh ,  Beak-Hyung Cho ,  Woo-Yeong Cho

    发明人： Kwang-Jin Lee ,  Sang-Beom Kang ,  Hyung-Rok Oh ,  Beak-Hyung Cho ,  Woo-Yeong Cho

    IPC分类号： G11C7/06

    CPC分类号： G11C13/0069 ,  G11C7/06 ,  G11C7/1006 ,  G11C13/0004 ,  G11C2013/0076 ,  G11C2211/5647

    摘要： Embodiments of the invention provide devices or methods that include a status bit representing an inversion of stored data. New data is written to selected cells, the new data is selectively inverted, and the status bit is selectively toggled, based on a comparison between pre-existing data and new data associated with a write command. A benefit of embodiments of the invention is that fewer memory cells must be activated in many instances (when compared to conventional art approaches). Moreover, embodiments of the invention may also reduce the average amount of activation current required to write to variable resistive memory devices and other memory device types.

    摘要翻译： 本发明的实施例提供了包括表示存储数据的反转的状态位的设备或方法。 将新数据写入所选择的单元，根据预先存在的数据与与写命令相关联的新数据之间的比较，选择性地反转新数据并选择性地切换状态位。 本发明的实施例的优点在于，在许多情况下（与传统技术方法相比），必须激活更少的存储器单元。 此外，本发明的实施例还可以减少写入可变电阻存储器件和其他存储器件类型所需的平均激活电流量。

    Semiconductor memory device and method for reducing cell activation during write operations
    6.
    发明申请
    Semiconductor memory device and method for reducing cell activation during write operations 有权
    用于在写入操作期间减少电池激活的半导体存储器件和方法

    公开(公告)号：US20080101131A1

    公开(公告)日：2008-05-01

    申请号：US11790146

    申请日：2007-04-24

    申请人： Kwang-Jin Lee ,  Sang-Beom Kang ,  Hyung-Rok Oh ,  Beak-Hyung Cho ,  Woo-Yeong Cho

    发明人： Kwang-Jin Lee ,  Sang-Beom Kang ,  Hyung-Rok Oh ,  Beak-Hyung Cho ,  Woo-Yeong Cho

    IPC分类号： G11C7/06

    CPC分类号： G11C13/0069 ,  G11C7/06 ,  G11C7/1006 ,  G11C13/0004 ,  G11C2013/0076 ,  G11C2211/5647

    摘要： Embodiments of the invention provide devices or methods that include a status bit representing an inversion of stored data. New data is written to selected cells, the new data is selectively inverted, and the status bit is selectively toggled, based on a comparison between pre-existing data and new data associated with a write command. A benefit of embodiments of the invention is that fewer memory cells must be activated in many instances (when compared to conventional art approaches). Moreover, embodiments of the invention may also reduce the average amount of activation current required to write to variable resistive memory devices and other memory device types.

    摘要翻译： 本发明的实施例提供了包括表示存储数据的反转的状态位的设备或方法。 将新数据写入所选择的单元，根据预先存在的数据与与写命令相关联的新数据之间的比较，选择性地反转新数据并选择性地切换状态位。 本发明的实施例的优点在于，在许多情况下（与传统技术方法相比），必须激活更少的存储器单元。 此外，本发明的实施例还可以减少写入可变电阻存储器件和其他存储器件类型所需的平均激活电流量。

    Semiconductor memory devices for alternately selecting bit lines
    10.
    发明授权
    Semiconductor memory devices for alternately selecting bit lines 有权
    用于交替选择位线的半导体存储器件

    公开(公告)号：US09183910B2

    公开(公告)日：2015-11-10

    申请号：US13907223

    申请日：2013-05-31

    申请人： Yun-Sang Lee ,  Dong-Seok Kang ,  Sang-Beom Kang ,  Chan-Kyung Kim ,  Chul-Woo Park ,  Dong-Hyun Sohn ,  Hyung-Rok Oh

    发明人： Yun-Sang Lee ,  Dong-Seok Kang ,  Sang-Beom Kang ,  Chan-Kyung Kim ,  Chul-Woo Park ,  Dong-Hyun Sohn ,  Hyung-Rok Oh

    IPC分类号： G11C11/16 ,  G11C7/12

    CPC分类号： G11C11/1653 ,  G11C7/12 ,  G11C11/16 ,  G11C11/161 ,  G11C11/1673 ,  G11C11/1675 ,  G11C11/1693 ,  G11C11/1697

    摘要： A semiconductor memory device includes a cell array including one or more bank groups, where each of the one or more bank groups includes a plurality of banks and each of the plurality of banks includes a plurality of spin transfer torque magneto resistive random access memory (STT-MRAM) cells. The semiconductor memory device further includes a source voltage generating unit for applying a voltage to a source line connected to the each of the plurality of STT-MRAM cells, and a command decoder for decoding a command from an external source in order to perform read and write operations on the plurality of STT-MRAM cells. The command includes a combination of at least one signal of a row address strobe (RAS), a column address strobe (CAS), a chip selecting signal (CS), a write enable signal (WE), and a clock enable signal (CKE).

    摘要翻译： 半导体存储器件包括一个单元阵列，其包括一个或多个存储体组，其中一个或多个存储体组中的每个组包括多个存储体，并且多个存储体中的每一个存储体包括多个自旋传递转矩磁阻随机存取存储器（STT -MRAM）细胞。 半导体存储器件还包括用于向连接到多个STT-MRAM单元中的每一个的源极线施加电压的源极电压产生单元，以及用于对来自外部源的命令进行解码的命令解码器，以执行读取和 对多个STT-MRAM单元进行写入操作。 该命令包括行地址选通（RAS），列地址选通（CAS），片选信号（CS），写使能信号（WE）和时钟使能信号（CKE）的至少一个信号 ）。