公开(公告)号：US20090302891A1

公开(公告)日：2009-12-10

申请号：US12326990

申请日：2008-12-03

Applicant: Kyung-Hoon Kim ,  Dae-Han Kwon ,  Taek-Sang Song

Inventor： Kyung-Hoon Kim ,  Dae-Han Kwon ,  Taek-Sang Song

IPC: H03K19/0175

CPC classification number: H03K19/018528

Abstract: There is provided an output driver, which includes a pre-driver configured to generate a main driving control signal in response to a data signal, a main driver configured to drive an output terminal in response to the main driving control signal, an auxiliary driving control signal generator configured to generate an auxiliary driving control signal having an activation interval corresponding to the data signal and an interval control signal, and an auxiliary driver configured to drive the output terminal in response to the auxiliary driving control signal.

Abstract translation: 提供了一种输出驱动器，其包括配置为响应于数据信号产生主驱动控制信号的预驱动器，配置成响应于主驱动控制信号驱动输出端的主驱动器，辅助驱动控制 信号发生器，其被配置为产生具有与数据信号和间隔控制信号对应的激活间隔的辅助驱动控制信号，以及配置为响应于辅助驱动控制信号来驱动输出端子的辅助驱动器。

公开(公告)号：US20090207158A1

公开(公告)日：2009-08-20

申请号：US12264724

申请日：2008-11-04

Applicant: Seong-Il PARK ,  Kyung-Hoon Kim

Inventor： Seong-Il PARK ,  Kyung-Hoon Kim

IPC: G06F3/038 ,  G09G3/30

CPC classification number: G09G3/3233 ,  G09G2300/0819 ,  G09G2300/0861 ,  G09G2310/061 ,  G09G2320/0261

Abstract: A display device includes a light emitting element to emit light having an intensity that varies depending on a magnitude of a driving current, a capacitor connected between a first node and a second node, a driving transistor having an input terminal connected to a first voltage, an output terminal, and a control terminal connected to the second node, a first switching unit to connect a data voltage and a second voltage to the first node, a second switching unit to switch a connection between the second voltage and the second node, a third switching unit to connect the second node and the light emitting element to the output terminal of the driving transistor, and a fourth switching unit to switch a connection between the control terminal and the input terminal of the driving transistor.

Abstract translation: 显示装置包括：发光元件，其发光强度根据驱动电流的大小而变化，连接在第一节点和第二节点之间的电容器;驱动晶体管，具有与第一电压相连的输入端; 输出端子和连接到第二节点的控制端子，将数据电压和第二电压连接到第一节点的第一开关单元，用于切换第二电压和第二节点之间的连接的第二开关单元， 第三开关单元，用于将第二节点和发光元件连接到驱动晶体管的输出端;以及第四开关单元，用于切换控制端子与驱动晶体管的输入端子之间的连接。

公开(公告)号：US20090168944A1

公开(公告)日：2009-07-02

申请号：US12344552

申请日：2008-12-28

Applicant: Taek-Sang Song ,  Kyung-Hoon Kim ,  Dae-Han Kwon ,  Dae-Kun Yoon

Inventor： Taek-Sang Song ,  Kyung-Hoon Kim ,  Dae-Han Kwon ,  Dae-Kun Yoon

IPC: H03D3/24

CPC classification number: H03L7/095 ,  G01R29/0273 ,  H03K5/153 ,  H03K2005/00065 ,  H03K2005/00071 ,  Y10S331/02

Abstract: A low pass filter includes a driver unit configured to output a voltage proportional to an input pulse width, a charge/discharge unit configured to charge the output voltage of the driver unit, a comparator unit configured to compare an output voltage of the charge/discharge unit with a reference value to output a square wave signal, and a switching unit configured to switch the charge/discharge unit to an operation state, based on a bandwidth expansion signal.

Abstract translation: 低通滤波器包括被配置为输出与输入脉冲宽度成比例的电压的驱动器单元，被配置为对驱动器单元的输出电压进行充电的充电/放电单元，被配置为比较充电/放电的输出电压 具有参考值的单元以输出方波信号;以及切换单元，被配置为基于带宽扩展信号将充电/放电单元切换到操作状态。

公开(公告)号：US20090128208A1

公开(公告)日：2009-05-21

申请号：US12263690

申请日：2008-11-03

Applicant: Taek-Sang Song ,  Kyung-Hoon Kim ,  Dae-Han Kwon ,  Dae-Kun Yoon

Inventor： Taek-Sang Song ,  Kyung-Hoon Kim ,  Dae-Han Kwon ,  Dae-Kun Yoon

IPC: H03K3/017

CPC classification number: H03K3/017

Abstract: Apparatus for detecting duty ratio of signals in semiconductor device circuit includes a circuit for detecting a duty ratio of signals in a semiconductor device includes a comparing unit which compares a duty cycle of first and second input clock signals input differentially and generates a first output signal and a second output signal, a latching unit which stores the first and second output signals and generates a detected signal corresponding to the first and second output signals, and an adjusting unit which receives the first and the second output signals, and transmits the first and the second output signals to the latching unit based on a voltage level difference of the first and second output signals.

Abstract translation: 用于检测半导体器件电路中的信号占空比的装置包括用于检测半导体器件中的信号的占空比的电路，包括比较单元，其比较差分输入的第一和第二输入时钟信号的占空比并产生第一输出信号， 第二输出信号，存储第一和第二输出信号并产生对应于第一和第二输出信号的检测信号的锁存单元，以及接收第一和第二输出信号的调整单元，并且发送第一和第二输出信号 基于第一和第二输出信号的电压电平差，向锁存单元输出第二输出信号。

公开(公告)号：US20090116601A1

公开(公告)日：2009-05-07

申请号：US12005850

申请日：2007-12-28

Applicant: Kyung-Hoon Kim ,  Jong-Ho Kang ,  Yong-Ki Kim ,  Dae-Han Kwon ,  Sang-Yeon Byeon

Inventor： Kyung-Hoon Kim ,  Jong-Ho Kang ,  Yong-Ki Kim ,  Dae-Han Kwon ,  Sang-Yeon Byeon

IPC: H04L7/00

CPC classification number: G11C7/22 ,  G11C7/222 ,  H03L7/089 ,  H03L7/091 ,  H03L7/093

Abstract: A clock data recovery (CDR) circuit occupies a small area required in a high-integration semiconductor device, electronic device and system and is easy in design modification. The CDR circuit includes a digital filter configured to filter phase comparison result signals received during predetermined periods and output control signals, a driver configured to control the digital filter by adjusting the predetermined periods, and an input/output circuit configured to recognize an input and output of data and clock in response to the control signals.

Abstract translation: 时钟数据恢复（CDR）电路占据了高集成度半导体器件，电子器件和系统所需的较小面积，并且易于进行设计修改。 CDR电路包括：数字滤波器，被配置为滤波在预定周期期间接收到的相位比较结果信号和输出控制信号;驱动器，被配置为通过调整预定周期来控制数字滤波器;以及输入/输出电路，被配置为识别输入和输出 的数据和时钟响应于控制信号。

公开(公告)号：US20090116598A1

公开(公告)日：2009-05-07

申请号：US12005492

申请日：2007-12-27

Applicant: Kyung-Hoon Kim ,  Yung-Ki Kim ,  Dae-Han Kwon ,  Taek-Sang Song

Inventor： Kyung-Hoon Kim ,  Yung-Ki Kim ,  Dae-Han Kwon ,  Taek-Sang Song

IPC: H04L7/02

CPC classification number: G11C29/02 ,  G11C7/1066 ,  G11C7/22 ,  G11C7/222 ,  G11C29/023 ,  G11C29/028

Abstract: A data clock frequency divider circuit includes a training decoder and a frequency divider. The training decoder outputs a clock alignment training signal, which is indicative of the start of a clock alignment training, in response to a command and an address of a mode register set. The frequency divider, which is reset in response to an output of the training decoder, receives an internal data clock to divide a frequency of the internal data clock in half. The data clock frequency divider circuit secures a sufficient operating margin so that a data clock and a system clock are aligned within a pre-set clock training operation time by resetting the data clock to correspond to a timing in which the clock training operation starts, thereby providing a clock training for a high-speed system.

Abstract translation: 数据时钟分频器电路包括训练解码器和分频器。 响应于模式寄存器组的命令和地址，训练解码器输出表示时钟对准训练的开始的时钟对准训练信号。 响应于训练解码器的输出复位的分频器接收内部数据时钟以将内部数据时钟的频率分成两半。 数据时钟分频器电路确保足够的操作余量，使得数据时钟和系统时钟在预设的时钟训练操作时间内对齐，通过复位数据时钟以对应于时钟训练操作开始的定时，由此 为高速系统提供时钟训练。

公开(公告)号：US20090086881A1

公开(公告)日：2009-04-02

申请号：US12005933

申请日：2007-12-28

Applicant: Dae-Kun Yoon ,  Kyung-Hoon Kim ,  Dae-Han Kwon ,  Taek-Sang Song

Inventor： Dae-Kun Yoon ,  Kyung-Hoon Kim ,  Dae-Han Kwon ,  Taek-Sang Song

IPC: G06M3/00

CPC classification number: G06M3/12

Abstract: A counter with overflow prevention capability includes a counting unit configured to count an output code in response to an input signal and an overflow preventing unit configured to control the counting unit to stop counting the output code when a current value of the output code is a maximum value but a previous value thereof is not the maximum value.

Abstract translation: 具有防溢能力的计数器包括：计数单元，被配置为响应于输入信号对输出代码进行计数;以及溢出防止单元，被配置为当输出代码的当前值为最大值时，控制计数单元停止计数输出代码 值，但其前一值不是最大值。

公开(公告)号：US07489159B2

公开(公告)日：2009-02-10

申请号：US11641856

申请日：2006-12-20

Applicant: Kyung Hoon Kim

Inventor： Kyung Hoon Kim

IPC: H03K19/003

CPC classification number: G11C8/08 ,  G11C7/02 ,  G11C7/08 ,  G11C7/12 ,  G11C11/406 ,  G11C11/4091 ,  G11C11/4094 ,  G11C29/02 ,  G11C29/023 ,  G11C29/028 ,  G11C29/50008 ,  G11C2029/1202 ,  G11C2211/4065

Abstract: A circuit for controlling a driver of a semiconductor memory apparatus includes at least one driving unit in which impedance is set according to a code value, an impedance adjusting unit that outputs a first code and a second code for setting the impedance of the at least one driving unit, a driving reinforcing control unit that outputs an adjustment code for a time corresponding to timing data, and a driving reinforcing unit that outputs a first reinforcing code and a second reinforcing code obtained by adjusting the first code and the second code using the adjustment code, such that a driving capability of the at least one driving unit is reinforced.

Abstract translation: 用于控制半导体存储装置的驱动器的电路包括至少一个驱动单元，其中根据代码值设置阻抗;阻抗调整单元，输出第一代码和第二代码，用于设置至少一个 驱动单元，输出对应于定时数据的时间的调整代码的驱动加强控制单元，以及驱动加强单元，其输出通过使用调整来调整第一代码和第二代码而获得的第一加强代码和第二加强代码 代码，使得至少一个驱动单元的驱动能力得到加强。

公开(公告)号：US20090033392A1

公开(公告)日：2009-02-05

申请号：US12284060

申请日：2008-09-18

Applicant: Kyung-Hoon Kim

Inventor： Kyung-Hoon Kim

IPC: H03L7/00

CPC classification number: G11C7/222 ,  G11C7/22 ,  H03L7/0814 ,  H03L7/085

Abstract: A delay locked loop can remove a jitter component that inevitably occurs due to feedback latency in the conventional DLL. That is, the present invention has benefit of removing the jitter component by controlling the delay lines based on the predicted data. The delay locked loop includes a pattern detecting unit for generating and storing a noise pattern by detecting inputted noise data, a pre-delay control unit for determining a delay amount depending on the output of the pattern detecting unit, and a pre-delay line for delaying an internal clock depending on the delay amount that is determined by the pre-delay control means.

Abstract translation: 延迟锁定环可以消除由于常规DLL中的反馈等待时间而不可避免地发生的抖动分量。 也就是说，本发明通过基于预测数据控制延迟线来消除抖动分量的益处。 延迟锁定环包括：图案检测单元，用于通过检测输入的噪声数据产生和存储噪声模式;预延迟控制单元，用于根据模式检测单元的输出确定延迟量;以及预延迟线， 根据由预延迟控制装置确定的延迟量来延迟内部时钟。

公开(公告)号：US07429871B2

公开(公告)日：2008-09-30

申请号：US11477543

申请日：2006-06-30

Applicant: Dong-keun Kim ,  Kyung-Hoon Kim

Inventor： Dong-keun Kim ,  Kyung-Hoon Kim

IPC: H03K19/003

CPC classification number: H04L25/0298

Abstract: An on die termination (ODT) control device includes a mode register set for generating a clock control signal based on mode set information; a clock control unit for receiving an internal clock signal and a delay locked loop (DLL) clock signal and outputting an intermediate internal clock signal and an intermediate DLL clock signal in response to the clock control signal; and an ODT control unit for controlling an ODT block by receiving an ODT control signal in response to the intermediate internal clock signal and the intermediate DLL clock signal.

Abstract translation: 芯片终端（ODT）控制装置包括：模式寄存器组，用于基于模式集信息产生时钟控制信号; 时钟控制单元，用于接收内部时钟信号和延迟锁定环（DLL）时钟信号，并响应于时钟控制信号输出中间内部时钟信号和中间DLL时钟信号; 以及ODT控制单元，用于响应于中间内部时钟信号和中间DLL时钟信号而接收ODT控制信号来控制ODT块。