公开(公告)号：US20040068383A1

公开(公告)日：2004-04-08

申请号：US10610343

申请日：2003-06-30

Applicant: STMICROELECTRONICS S.A. ,  STMICROELECTRONICS LTD

Inventor： Hitesh Shah ,  Laurent Perier

IPC: G06F019/00

CPC classification number: H03L1/00

Abstract: A chip includes CPU (12), memories (13,14) for programs and data, peripheral units (18,19) for interacting with the outside world, and an internal RC oscillator (17) for providing clock signals. One of the peripheral units (18) includes a timer counter incremented at a frequency derived from the RC oscillator. The method does not try to change the frequency of the RC oscillator. Instead, an external calibration source (21) is connected to a capture input of the timer unit to provide a signal having a reference frequency, e.g. the mains frequency. The counter is sampled on active edges of that signal, and the sampled values are processed to derive a calibration ratio. After these calibration steps, a software correction is applied to parameters handled by programs stored in memory based on the calibration ratio to compensate for frequency variations of the RC oscillator.

Abstract translation: 芯片包括CPU（12），用于程序和数据的存储器（13,14），用于与外界相互作用的外围单元（18,19）和用于提供时钟信号的内部RC振荡器（17）。 外围单元（18）中的一个包括以从RC振荡器得到的频率递增的定时器计数器。 该方法不会改变RC振荡器的频率。 相反，外部校准源（21）连接到定时器单元的捕获输入，以提供具有参考频率的信号，例如， 电源频率。 在该信号的有效边沿对计数器进行采样，并处理采样值以导出校准比。 在这些校准步骤之后，基于校准比率对存储在存储器中的程序处理的参数应用软件校正以补偿RC振荡器的频率变化。

公开(公告)号：US20040046192A1

公开(公告)日：2004-03-11

申请号：US10454361

申请日：2003-06-04

Applicant: STMICROELECTRONICS S.A. ,  COMMISSARIAT A L'ENERGIE ATOMIQUE

Inventor： Damien Lenoble ,  Isabelle Guilmeau

IPC: H01L029/76

CPC classification number: H01L29/6659 ,  H01L21/2652 ,  H01L29/6656

Abstract: Process for fabricating a transistor comprises producing source and drain extension regions, consisting in forming a gate region on a semiconductor substrate and in implanting dopants into the semiconductor substrate on either side of and at a certain distance from the gate of the transistor. The producing of the source and drain extension regions consists in forming an intermediate layer (Cl) on the sidewalls of the gate (GR) and on the surface of the semiconductor substrate. This intermediate layer is formed from a material that is less dense than silicon dioxide. The implantation of dopants (IMP) is carried out through that part of the intermediate layer that is located on the semiconductor substrate.

Abstract translation: 用于制造晶体管的工艺包括产生源极和漏极延伸区域，其包括在半导体衬底上形成栅极区域，并且在晶体管的栅极的任一侧和距离晶体管的栅极的任意一侧离开半导体衬底中注入掺杂剂。 源极和漏极延伸区域的产生在于在栅极（GR）的侧壁上和半导体衬底的表面上形成中间层（Cl）。 该中间层由比二氧化硅致密的材料形成。 掺杂剂（IMP）的注入通过位于半导体衬底上的部分中间层进行。

公开(公告)号：US20040027098A1

公开(公告)日：2004-02-12

申请号：US10460039

申请日：2003-06-11

Applicant: STMICROELECTRONICS S.A.

Inventor： Jerome Nebon

IPC: G05F001/613

CPC classification number: H02M3/1588 ,  Y02B70/1466

Abstract: A control device is provided for a switching power supply having an output that supplies an output voltage. The switching power supply includes an inductor and two changeover switches for controlling coupling of the inductor. The control device includes a first capacitor for charging with continuous current from a 0 V voltage level, a second capacitor for discharging of the continuous current from a predetermined voltage level that is greater than the voltage level of a DC power supply, and a comparison circuit. The comparison circuit compares the output voltage of the switching power supply with voltage levels of the first and second capacitors and generates control signals for controlling the two changeover switches of the switching power supply. Also provided are switching power supplies having such control devices and a method for controlling a switching power supply.

Abstract translation: 为具有提供输出电压的输出的开关电源提供控制装置。 开关电源包括电感器和用于控制电感器耦合的两个转换开关。 控制装置包括用于从0V电压电平充电的连续电流的第一电容器，用于从大于DC电源的电压电平的预定电压电平放电连续电流的第二电容器，以及比较电路 。 比较电路将开关电源的输出电压与第一和第二电容器的电压电平进行比较，并产生用于控制开关电源的两个转换开关的控制信号。 还提供了具有这种控制装置的开关电源和用于控制开关电源的方法。

公开(公告)号：US20040016968A1

公开(公告)日：2004-01-29

申请号：US10409653

申请日：2003-04-08

Applicant: STMICROELECTRONICS S.A.

Inventor： Philippe Coronel ,  Stephane Monfray ,  Thomas Skotnicki

IPC: H01L021/84 ,  H01L031/0392

CPC classification number: H01L29/66772 ,  H01L29/78648 ,  H01L29/78654

Abstract: A semiconductor device is provided that includes a semiconductor channel region extending above a semiconductor substrate in a longitudinal direction between a semiconductor source region and a semiconductor drain region, and a gate region extending in the transverse direction, coating the channel region, and insulated from the channel region. The source, channel, and drain regions are formed in a continuous semiconductor layer that is approximately plane and parallel to the upper surface of the substrate. Additionally, the source, drain, and gate regions are coated in an insulating coating so as to provide electrical insulation between the gate region and the source and drain regions, and between the substrate and the source, drain, gate, and channel regions. Also provided is an integrated circuit that includes such a semiconductor device, and a method for manufacturing such a semiconductor device.

Abstract translation: 提供一种半导体器件，其包括在半导体源极区域和半导体漏极区域之间沿纵向方向在半导体衬底上方延伸的半导体沟道区域和在横向方向上延伸的栅极区域，涂覆沟道区域并与 渠道区域。 源极，沟道和漏极区域形成在大致平面并平行于衬底的上表面的连续半导体层中。 此外，源极，漏极和栅极区域被涂覆在绝缘涂层中，以便在栅极区域和源极和漏极区域之间以及衬底与源极，漏极，栅极和沟道区域之间提供电绝缘。 还提供了一种包括这种半导体器件的集成电路及其制造方法。

公开(公告)号：US20030174249A1

公开(公告)日：2003-09-18

申请号：US10356350

申请日：2003-01-30

Applicant: STMicroelectronics S.A.

Inventor： Lionel Grillo

IPC: H03M001/12

CPC classification number: H03M1/1295 ,  H04N5/18

Abstract: A calibration device for a video circuit input stage comprises an analog-to-digital converter and an input capacitor constantly discharged by a power source and recharged by a charging circuit by means of a first and a second charging current. The charging circuit is controlled by a central processing unit receiving an estimate of the variation between the converter's output code and a clamp value.

Abstract translation: 用于视频电路输入级的校准装置包括模数转换器和由电源恒定放电并由充电电路借助于第一和第二充电电流再充电的输入电容器。 充电电路由接收对转换器的输出代码和钳位值之间的变化的估计的中央处理单元控制。

公开(公告)号：US20030160650A1

公开(公告)日：2003-08-28

申请号：US10351601

申请日：2003-01-24

Applicant: STMicroelectronics S.A.

Inventor： Pierre Rizzo

IPC: H03D001/00

CPC classification number: G06K19/0723 ,  H03D1/18 ,  H03K5/082

Abstract: A demodulator for an amplitude modulated alternating signal includes a peak detection circuit for extracting the reference modulating signal from the amplitude modulated alternating signal, and a first translation circuit for offsetting the level of the reference modulating signal by a value equal to the DC component to obtain an offset reference modulated signal. A comparison threshold generator circuit generates a comparison threshold to locate the start and the end of the modulation, and a comparator circuit compares the offset reference modulating signal with the comparison threshold for providing signals that cross the comparison threshold. An unregulated supply circuit provides a supply voltage to the different circuits.

Abstract translation: 用于幅度调制交替信号的解调器包括用于从调幅交替信号中提取参考调制信号的峰值检测电路和用于将参考调制信号的电平抵消等于DC分量的值的第一平移电路，以获得 偏移参考调制信号。 比较阈值发生器电路产生比较阈值以定位调制的开始和结束，并且比较器电路将偏移参考调制信号与比较阈值进行比较，以提供跨越比较阈值的信号。 不稳定的电源电路为不同的电路提供电源电压。

公开(公告)号：US20030119219A1

公开(公告)日：2003-06-26

申请号：US10308482

申请日：2002-12-03

Applicant: STMICROELECTRONICS S.A.

Inventor： Alexis Farcy ,  Philippe Coronel ,  Pascal Ancey ,  Joaquin Torres

IPC: H01L021/00 ,  H01L021/44 ,  H01L021/48 ,  H01L021/50

CPC classification number: B81C1/0023 ,  B29C2043/5825

Abstract: The fabrication of an integrated circuit includes a first phase of producing an electronic chip and a second phase of producing at least one auxiliary component placed above the chip and of producing a protective cover which covers the auxiliary component. The first phase of producing the chip is effected from a first semiconductor substrate and comprises the formation of a cavity lying in a chosen region of the chip and emerging at the upper surface of the chip. The second production phase includes the production of the auxiliary component from a second semiconductor substrate, separate from the first, and then the placement in the cavity of the auxiliary component supported by the second substrate and the mutual adhesion of the second substrate to the upper surface of the chip lying outside the cavity. The second substrate then also forms the protective cover.

Abstract translation: 集成电路的制造包括制造电子芯片的第一阶段和产生放置在芯片上方的至少一个辅助部件并产生覆盖辅助部件的保护盖的第二阶段。 制造芯片的第一阶段从第一半导体衬底实现，并且包括形成位于芯片的选定区域中并且出现在芯片的上表面处的空腔。 第二生产阶段包括从第二半导体衬底生产辅助部件，与第一半导体衬底分离，然后放置在由第二衬底支撑的辅助部件的空腔中，以及将第二衬底与上表面的相互粘合 的芯片位于腔外。 第二基板然后也形成保护盖。

公开(公告)号：US20030118129A1

公开(公告)日：2003-06-26

申请号：US10153000

申请日：2002-05-22

Applicant: STMICROELECTRONICS S.A.

Inventor： Marc Joisson ,  Luc Garcia ,  Sebastien Leveque

IPC: H03D003/00 ,  H04L027/14 ,  H04B001/16

CPC classification number: H04L27/1563

Abstract: A receiver of a frequency-modulated signal representing a digital signal includes a down conversion unit or frequency translation unit to lower the frequency of the frequency-modulated signal and a digital demodulator to regenerate the digital signal from the lowered-frequency signal. The receiver furthermore includes a counter circuit to determine the number of periods of a reference signal from the frequency translation unit during a period of the lowered-frequency signal. The digital demodulator includes a computer unit to compute the period of the lowered-frequency signal from the number of periods of the reference signal.

Abstract translation: 表示数字信号的频率调制信号的接收机包括降频变频单元或频率转换单元，以降低频率调制信号的频率，以及数字解调器，以从低频信号再生数字信号。 接收器还包括一个计数器电路，用于在降频信号的周期期间确定来自频率转换单元的参考信号的周期数。 数字解调器包括计算机单元，用于根据参考信号的周期数来计算降频信号的周期。

公开(公告)号：US20030102577A1

公开(公告)日：2003-06-05

申请号：US10315870

申请日：2002-12-09

Applicant: STMicroelectronics S.A.

Inventor： Yvon Gris

IPC: H01L027/088

CPC classification number: H01L29/66242 ,  H01L29/66272

Abstract: A method for defining, on the upper surface of a substrate, two self-aligned areas, including the steps of depositing a protective layer; depositing a covering layer; opening the protective and covering layers at a location substantially corresponding to the desired border of the two areas; forming a spacer along the side of the opening, this spacer having a rear portion against said border and an opposite front portion; opening the protective and covering layers behind the rear portion of the spacer; and removing the protection layer to reach the rear portion of the spacer; whereby two self-aligned areas are defined on either side of the spacer length.

公开(公告)号：US20030095453A1

公开(公告)日：2003-05-22

申请号：US10299965

申请日：2002-11-19

Applicant: STMicroelectronics S.A.

Inventor： Francesco La Rosa

IPC: G11C007/00

CPC classification number: G11C7/062 ,  G11C16/28 ,  G11C2207/063

Abstract: The present invention relates to a read amplifier (SA2) comprising a read stage (RDST), a reference stage (RFST) and a differential output stage comprising PMOS and NMOS type transistors. According to the present invention, the transistors of the differential stage (DIFST2) comprise only one PMOS transistor (TP3) and one NMOS transistor (TN3) in series, the PMOS transistor (TP3) having its gate linked to one node of the read stage (RDST), the NMOS transistor (TN3) having its gate linked to one node of the reference stage (RFST), the mid-point of the PMOS and NMOS transistors of the differential stage forming a data output node (DATAOUT) of the read amplifier. The read amplifier according to the present invention has the combined advantages of a short read time and a low electrical consumption. Application to EPROM, EEPROM and FLASH type non-volatile memories.

Abstract translation: 本发明涉及包括读阶段（RDST），参考级（RFST）和包括PMOS和NMOS型晶体管的差分输出级的读放大器（SA2）。 根据本发明，差分级（DIFST2）的晶体管仅包括串联的一个PMOS晶体管（TP3）和一个NMOS晶体管（TN3），PMOS晶体管（TP3）的栅极连接到读取级的一个节点 （RDST），其栅极连接到参考级（RFST）的一个节点的NMOS晶体管（TN3），差分级的PMOS和NMOS晶体管的中点形成读取的数据输出节点（DATAOUT） 放大器 根据本发明的读取放大器具有短的读取时间和低的电力消耗的组合优点。 应用于EPROM，EEPROM和FLASH型非易失性存储器。