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公开(公告)号：US20240045762A1
公开(公告)日：2024-02-08
申请号：US17883051
申请日：2022-08-08
Applicant: Micron Technology, Inc.
Inventor： Nitul Gohain , Jonathan S. Parry , Reshmi Basu
CPC classification number: G06F11/1068 , G06F11/0772 , G06F3/0659 , G06F3/0619 , G06F3/0679
Abstract: Methods, systems, and devices for queue management for a memory system are described. The memory system may include a first decoder associated with a first error control capability and a second decoder associated with a second error control capability. The memory system may receive a command and identify an expected latency for performing an error control operation on the command. The memory system may determine whether to assign the command to a first queue associated with the first decoder or a second queue associated with the second decoder based at least in part on the expected latency for processing the command using the first decoder. Upon assigning the command to a decoder, the command may be processed by the first queue or the second queue.
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公开(公告)号：US11847353B2
公开(公告)日：2023-12-19
申请号：US17649268
申请日：2022-01-28
Applicant: Micron Technology, Inc.
Inventor： Jonathan S. Parry , Christian M. Gyllenskog , Luca Porzio
IPC: G06F3/06
CPC classification number: G06F3/0659 , G06F3/0619 , G06F3/0625 , G06F3/0634 , G06F3/0679
Abstract: Methods, systems, and devices for suspend operation with data transfer to a host system are described. A host system may transmit a read command to a memory system operating in a first mode of operation (e.g., a standard mode associated with a nominal power consumption) indicating for the memory system to transition to a second mode of operation (e.g., a suspend mode associated with a decreased power consumption). Here, the memory system may transmit an image of the memory system stored in volatile memory to the host system and transition the memory system to the second mode. Additionally, the host system may transmit, to the memory system operating in the second mode, a write command including the image and indicating for the memory system to transition to the first mode. Here, the memory system may write the image to the volatile memory and transition to the first mode.
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公开(公告)号：US11829623B2
公开(公告)日：2023-11-28
申请号：US17678459
申请日：2022-02-23
Applicant: Micron Technology, Inc.
Inventor： Kishore Kumar Muchherla , Ashutosh Malshe , Jianmin Huang , Jonathan S. Parry , Xiangang Luo
IPC: G06F3/06
CPC classification number: G06F3/064 , G06F3/0613 , G06F3/0619 , G06F3/0659 , G06F3/0679
Abstract: A system can include a memory device, and a processing device, operatively coupled with the memory device, to perform operations of writing a first portion of data to one or more complete translation units of the memory device using a first number of logical levels per memory cell and writing a second portion of the data to one or more incomplete translation units of the memory device using the first number of logical levels per memory cell. The operations can also include writing a third portion of the data to one or more complete translation units of the memory device using a second number of logical levels per memory cell that exceeds the first number of logical levels per memory cell.
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公开(公告)号：US11797380B2
公开(公告)日：2023-10-24
申请号：US17647700
申请日：2022-01-11
Applicant: Micron Technology, Inc.
Inventor： David Aaron Palmer , Jonathan S. Parry
CPC classification number: G06F11/1068 , G06F11/0772 , G06F11/142 , G06F11/1417 , G06F12/0238
Abstract: Methods, systems, and devices for host-configurable error protection are described. A host system may receive an indication of a set of logical addresses supported by the memory system and available for use by the host system. The host system may divide the set of logical addresses into subsets of logical addresses. Each subset of logical addresses may be associated with a different type of data. The host system may determine an error protection configuration for a subset of logical addresses based at least in part on the type of data associated with the subset of logical addresses. The host system may then send to the memory system an indication of the subset of logical addresses and an indication of the error protection configuration for the subset of logical addresses.
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公开(公告)号：US11755237B2
公开(公告)日：2023-09-12
申请号：US17462228
申请日：2021-08-31
Applicant: Micron Technology, Inc.
Inventor： Jonathan S. Parry , Giuseppe Cariello , Reshmi Basu
IPC: G06F3/06
CPC classification number: G06F3/0655 , G06F3/0604 , G06F3/0679
Abstract: Methods, systems, and devices for overwriting at a memory system are described. A memory system may be configured to overwrite portions of a memory array with new data, which may be associated with omitting an erase operation. For example, write operations may be performed in accordance with a first demarcation configuration to store information at a portion of a memory array. A portion of a memory system may then determine to overwrite the portion of the memory array with different or updated information, which may include performing write operations in accordance with a second demarcation configuration. The second demarcation configuration may be associated with different cell characteristics for a one or more logic states, such as different distributions of stored charge or other cell property, different demarcation characteristics, different write operations, among other differences, which may support performing an overwrite operation without first performing an erase operation.
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Patent Agency Ranking
公开(公告)号：US20230281140A1
公开(公告)日：2023-09-07
申请号：US18114617
申请日：2023-02-27
Applicant: Micron Technology, Inc.
Inventor： Reshmi Basu , Jonathan S. Parry
CPC classification number: G06F13/1689 , G06F1/12
Abstract: Methods, systems, and devices for status check using signaling are described. A memory system may receive ready signals from memory dies. The ready signal may indicate whether a memory die is available to receive a command. The memory system may generate an indicator of whether the memory die is available based on values of ready signals. The memory system may output the indicator to a controller over one or more pins based on generating the indicator.
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公开(公告)号：US20230195350A1
公开(公告)日：2023-06-22
申请号：US17715799
申请日：2022-04-07
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Kishore Kumar Muchherla , Ashutosh Malshe , Peter Feeley , Jonathan S. Parry , Akira Goda , Jeffrey S. McNeil
CPC classification number: G06F3/065 , G06F3/0652 , G06F3/0659 , G06F3/0604 , G06F3/0673 , G06F12/0253
Abstract: A first set of host data items are programmed to first memory pages residing at a first region of a memory sub-system. A second set of host data items are programmed to second memory pages residing at the first region. A determination is made that a sequence at which the first set of host data items and the second set of host data items are programmed does not correspond to a target sequence associated with the memory sub-system. One or more of the first set of host data items are copied from one or more first memory pages to a second region of the memory sub-system that is allocated to store host data items initially programmed to first memory pages at the memory sub-system. One or more of the second set of host data items are copied from one or more second memory pages to a third region of the memory sub-system to store host data items that are programmed to second pages at the memory sub-system. A sequence of the copied one or more of the first set of host data items at the second region and the copied one or more of the second set of host data items at the third region correspond to the target sequence.
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公开(公告)号：US20230195341A1
公开(公告)日：2023-06-22
申请号：US17678459
申请日：2022-02-23
Applicant: Micron Technology, Inc.
Inventor： Kishore Kumar Muchherla , Ashutosh Malshe , Jianmin Huang , Jonathan S. Parry , Xiangang Luo
IPC: G06F3/06
CPC classification number: G06F3/064 , G06F3/0659 , G06F3/0619 , G06F3/0613 , G06F3/0679
Abstract: A system can include a memory device, and a processing device, operatively coupled with the memory device, to perform operations of writing a first portion of data to one or more complete translation units of the memory device using a first number of logical levels per memory cell and writing a second portion of the data to one or more incomplete translation units of the memory device using the first number of logical levels per memory cell. The operations can also include writing a third portion of the data to one or more complete translation units of the memory device using a second number of logical levels per memory cell that exceeds the first number of logical levels per memory cell.
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公开(公告)号：US20230066080A1
公开(公告)日：2023-03-02
申请号：US17463601
申请日：2021-09-01
Applicant: Micron Technology, Inc.
Inventor： Reshmi Basu , David A. Palmer , Jonathan S. Parry
Abstract: A method for data sequence prediction and resource allocation includes determining, by a memory system, a plurality of resource parameters associated with operation of the memory system and determining respective time intervals associated with usage patterns corresponding to the memory system, the respective time intervals being associated with one or more sets of the plurality of resource parameters. The method further includes determining, using the plurality of resource parameters, one or more weights for hidden layers of a neural network for the respective time intervals associated with the usage patterns and allocating computing resources within the memory system for use in execution of workloads based on the determined one or more weights for hidden layers of the neural network.
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公开(公告)号：US20230051212A1
公开(公告)日：2023-02-16
申请号：US17399406
申请日：2021-08-11
Applicant: Micron Technology, Inc.
Inventor： Jonathan S. Parry , David Aaron Palmer , Giuseppe Cariello
Abstract: Methods, systems, and devices for logic remapping techniques are described. A memory system may receive a write command to store information at a first logical address of the memory system. The memory system may generate a first entry of a logical-to-physical mapping that maps the first logical address with a first physical address that stores the information. The memory system may perform a defragmentation operation or other remapping operation. In such a defragmentation operation, the memory system may remap the first logical address to a second logical address, such that the second logical address is mapped to the first physical address. The memory system may generate a second entry of a logical-to-logical mapping that maps the first logical address with the second logical address.
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