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公开(公告)号：US20200013949A1
公开(公告)日：2020-01-09
申请号：US16056551
申请日：2018-08-07
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Ya-Sheng Feng , Hung-Chan Lin , Yu-Ping Wang , Yu-Chun Chen , Chiu-Jung Chiu
Abstract: A method for fabricating semiconductor device includes the steps of: forming a first inter-metal dielectric (IMD) layer on a substrate; forming a magnetic tunneling junction (MTJ) on the first IMD layer; forming a liner on the MTJ and the first IMD layer; removing part of the liner to form a spacer adjacent to the MTJ; and forming a second IMD layer on the first IMD layer.
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公开(公告)号：US20190341544A1
公开(公告)日：2019-11-07
申请号：US15996524
申请日：2018-06-04
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Ching-Wen Hung , Yu-Ping Wang
Abstract: A method for fabricating semiconductor device includes the steps of first providing a substrate having a magnetic tunnel junction (MTJ) region and an edge region, forming an first inter-metal dielectric (IMD) layer on the substrate, and then forming a first MTJ and a second MTJ on the first IMD layer, in which the first MTJ is disposed on the MTJ region while the second MTJ is disposed on the edge region. Next, a second IMD layer is formed on the first MTJ and the second MTJ.
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Patent Agency Ranking
公开(公告)号：US10374006B1
公开(公告)日：2019-08-06
申请号：US16055174
申请日：2018-08-06
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Chung-Liang Chu , Yu-Ping Wang , Yu-Ruei Chen
Abstract: The present invention provides a magnetic random access memory (MRAM) structure, the MRAM structure includes a transistor including a gate, a source and a drain, and a magnetic tunnel junction (MTJ) device, the MTJ device includes at least one free layer, an insulating layer and a fixed layer, the insulating layer is disposed between the free layer and the fixed layer, and the free layer is located above the insulating layer. The free layer of the MTJ device is electrically connected to a bit line (BL). The fixed layer of the MTJ device is electrically connected to the source of the transistor, and the drain of the transistor is electrically connected to a sense line (SL). And a first conductive via, directly contacting the MTJ device, the material of the first conductive via comprises tungsten.
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公开(公告)号：US10276633B1
公开(公告)日：2019-04-30
申请号：US15936377
申请日：2018-03-26
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Ching-Wen Hung , Yu-Ping Wang
IPC: H01L27/22 , H01L23/522 , H01L43/02 , H01L23/528 , H01L43/08 , H01L43/12 , H01F10/32 , H01F41/34 , G11C11/16
Abstract: A semiconductor device and method of forming the same, the semiconductor device includes a substrate, first plug, a magnetoresistive random access memory (MRAM) structure, a spacer layer, a seal layer and a first conductive pattern. The substrate has a first region and a second region, and the first plug is disposed on a dielectric layer disposed on the substrate, within the first region. The MRAM structure is disposed in the dielectric layer and electrically connected to the first plug. The spacer layer is disposed both within the first region and the second region, to cover the MRAM structure. The seal layer is disposed on the MRAM structure and the first plug, only within the first region. The first conductive pattern penetrates through the seal layer to electrically connect the MRAM structure.
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公开(公告)号：US09876116B2
公开(公告)日：2018-01-23
申请号：US15617099
申请日：2017-06-08
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Yu-Ping Wang , Jyh-Shyang Jenq , Yu-Hsiang Lin , Hsuan-Hsu Chen , Chien-Hao Chen , Yi-Han Ye
CPC classification number: H01L29/785 , H01L29/66795
Abstract: A semiconductor structure and a manufacturing method for the same are disclosed. The semiconductor structure includes a first gate structure, a second gate structure and a second dielectric spacer. Each of the first gate structure and the second gate structure adjacent to each other includes a first dielectric spacer. The second dielectric spacer is on one of opposing sidewalls of the first gate structure and without being disposed on the dielectric spacer of the second gate structure.
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公开(公告)号：US20170271504A1
公开(公告)日：2017-09-21
申请号：US15617099
申请日：2017-06-08
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Yu-Ping Wang , Jyh-Shyang Jenq , Yu-Hsiang Lin , Hsuan-Hsu Chen , Chien-Hao Chen , Yi-Han Ye
CPC classification number: H01L29/785 , H01L29/66795
Abstract: A semiconductor structure and a manufacturing method for the same are disclosed. The semiconductor structure includes a first gate structure, a second gate structure and a second dielectric spacer. Each of the first gate structure and the second gate structure adjacent to each other includes a first dielectric spacer. The second dielectric spacer is on one of opposing sidewalls of the first gate structure and without being disposed on the dielectric spacer of the second gate structure.
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公开(公告)号：US20170040435A1
公开(公告)日：2017-02-09
申请号：US14840041
申请日：2015-08-30
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Chun-Tsen Lu , Chien-Ming Lai , Lu-Sheng Chou , Ya-Huei Tsai , Ching-Hsiang Chiu , Yu-Tung Hsiao , Chen-Ming Huang , Kun-Ju Li , Yu-Ping Wang
IPC: H01L29/66 , H01L29/49 , C22C32/00 , H01L29/423
CPC classification number: H01L29/66545 , B32B1/00 , B32B18/00 , C22C32/0068 , H01L21/28088 , H01L29/4238 , H01L29/4966 , H01L29/511
Abstract: A semiconductor device is disclosed. The semiconductor device includes a substrate and a gate structure on the substrate. The gate structure includes a high-k dielectric layer on the substrate and a bottom barrier metal (BBM) layer on the high-k dielectric layer. Preferably, the BBM layer includes a top portion, a middle portion, and a bottom portion, in which the top portion being a nitrogen rich portion, and the middle portion and the bottom portion being titanium rich portions.
Abstract translation: 公开了一种半导体器件。 半导体器件包括衬底和衬底上的栅极结构。 栅极结构包括在衬底上的高k电介质层和高k电介质层上的底部阻挡金属（BBM）层。 优选地，BBM层包括顶部，中间部分和底部，其中顶部是富氮部分，中部和底部是富钛部分。
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