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公开(公告)号:US10008581B2
公开(公告)日:2018-06-26
申请号:US14840041
申请日:2015-08-30
Applicant: UNITED MICROELECTRONICS CORP.
Inventor: Chun-Tsen Lu , Chien-Ming Lai , Lu-Sheng Chou , Ya-Huei Tsai , Ching-Hsiang Chiu , Yu-Tung Hsiao , Chen-Ming Huang , Kun-Ju Li , Yu-Ping Wang
IPC: H01L23/48 , H01L23/52 , H01L29/40 , H01L29/66 , H01L29/423 , H01L29/49 , C22C32/00 , H01L29/51 , H01L21/28 , B32B1/00
CPC classification number: H01L29/66545 , B32B1/00 , B32B18/00 , C22C32/0068 , H01L21/28088 , H01L29/4238 , H01L29/4966 , H01L29/511
Abstract: A semiconductor device is disclosed. The semiconductor device includes a substrate and a gate structure on the substrate. The gate structure includes a high-k dielectric layer on the substrate and a bottom barrier metal (BBM) layer on the high-k dielectric layer. Preferably, the BBM layer includes a top portion, a middle portion, and a bottom portion, in which the top portion being a nitrogen rich portion, and the middle portion and the bottom portion being titanium rich portions.
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公开(公告)号:US10290723B2
公开(公告)日:2019-05-14
申请号:US15981913
申请日:2018-05-17
Applicant: UNITED MICROELECTRONICS CORP.
Inventor: Chun-Tsen Lu , Chien-Ming Lai , Lu-Sheng Chou , Ya-Huei Tsai , Ching-Hsiang Chiu , Yu-Tung Hsiao , Chen-Ming Huang , Kun-Ju Li , Yu-Ping Wang
Abstract: A semiconductor device includes a substrate and a gate structure on the substrate, in which the gate structure includes a high-k dielectric layer on the substrate and a bottom barrier metal (BBM) layer on the high-k dielectric layer. Preferably, the BBM layer includes a top portion, a middle portion, and a bottom portion, the middle portion being a nitrogen rich portion, the top portion and the bottom portion being titanium rich portions, and the top portion, the middle portion, and the bottom portion are of same material composition.
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公开(公告)号:US20180269308A1
公开(公告)日:2018-09-20
申请号:US15981913
申请日:2018-05-17
Applicant: UNITED MICROELECTRONICS CORP.
Inventor: Chun-Tsen Lu , Chien-Ming Lai , Lu-Sheng Chou , Ya-Huei Tsai , Ching-Hsiang Chiu , Yu-Tung Hsiao , Chen-Ming Huang , Kun-Ju Li , Yu-Ping Wang
CPC classification number: H01L29/66545 , B32B1/00 , B32B18/00 , C22C32/0068 , H01L21/28088 , H01L29/4238 , H01L29/4966 , H01L29/511
Abstract: A semiconductor device includes a substrate and a gate structure on the substrate, in which the gate structure includes a high-k dielectric layer on the substrate and a bottom barrier metal (BBM) layer on the high-k dielectric layer. Preferably, the BBM layer includes a top portion, a middle portion, and a bottom portion, the middle portion being a nitrogen rich portion, the top portion and the bottom portion being titanium rich portions, and the top portion, the middle portion, and the bottom portion are of same material composition.
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公开(公告)号:US09524967B1
公开(公告)日:2016-12-20
申请号:US15046458
申请日:2016-02-18
Applicant: UNITED MICROELECTRONICS CORP.
Inventor: Hao-Yeh Liu , Chien-Ming Lai , Yu-Ping Wang , Mon-Sen Lin , Ya-Huei Tsai , Ching-Hsiang Chiu
IPC: H01L27/088 , H01L27/092 , H01L21/8234
CPC classification number: H01L27/088 , H01L21/82345 , H01L21/823842 , H01L27/092
Abstract: A semiconductor device and a method of forming the same, the semiconductor device include a substrate, and a first transistor, a second transistor and a third transistor all disposed on the substrate. The first transistor includes a first channel, and a first barrier layer and a first work function layer stacked with each other on the first channel. The second transistor includes a second channel, and a second barrier layer and a second work function layer stacked with each other. The third transistor includes a third channel and a third barrier layer and a third work function layer stacked with each other on the third channel, wherein the first barrier layer, the second barrier layer and the third barrier layer have different nitrogen ratio. The first, the second and the third transistors have different threshold voltages, respectively.
Abstract translation: 半导体器件及其形成方法,所述半导体器件包括基板,以及全部设置在所述基板上的第一晶体管,第二晶体管和第三晶体管。 第一晶体管包括第一通道,以及在第一通道上彼此堆叠的第一势垒层和第一功函数层。 第二晶体管包括第二通道,以及彼此堆叠的第二阻挡层和第二功能层。 第三晶体管包括在第三沟道上彼此堆叠的第三沟道和第三势垒层和第三功函数层,其中第一势垒层,第二阻挡层和第三势垒层具有不同的氮比。 第一,第二和第三晶体管分别具有不同的阈值电压。
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公开(公告)号:US10818556B2
公开(公告)日:2020-10-27
申请号:US16223036
申请日:2018-12-17
Applicant: UNITED MICROELECTRONICS CORP.
Inventor: Hao-Yeh Liu , Jia-Feng Fang , Yu-Hsiang Lin , Ching-Hsiang Chiu , Chia-Wei Liu
IPC: H01L29/00 , H01L21/8234 , H01L21/762 , H01L21/3105 , H01L21/02 , H01L21/311 , H01L29/66 , H01L27/088 , H01L29/78 , H01L21/027
Abstract: A method for forming a semiconductor structure is provided. Multiple fins extending along a first direction are formed in a semiconductor substrate. The multiple fins includes a group of active fins, a pair of protection fins sandwiching about the group the active fins, and at least one dummy fin around the pair of protection fins. A fin cut process is performed to remove the at least one dummy fin around the pair of protection fins. After performing the fin cut process, trench isolation structures are formed within the trenches between the multiple fins. The trench isolation structures are subjected to an anneal process. After annealing the trench isolation structures, the pair of protection fins is removed.
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公开(公告)号:US20170040435A1
公开(公告)日:2017-02-09
申请号:US14840041
申请日:2015-08-30
Applicant: UNITED MICROELECTRONICS CORP.
Inventor: Chun-Tsen Lu , Chien-Ming Lai , Lu-Sheng Chou , Ya-Huei Tsai , Ching-Hsiang Chiu , Yu-Tung Hsiao , Chen-Ming Huang , Kun-Ju Li , Yu-Ping Wang
IPC: H01L29/66 , H01L29/49 , C22C32/00 , H01L29/423
CPC classification number: H01L29/66545 , B32B1/00 , B32B18/00 , C22C32/0068 , H01L21/28088 , H01L29/4238 , H01L29/4966 , H01L29/511
Abstract: A semiconductor device is disclosed. The semiconductor device includes a substrate and a gate structure on the substrate. The gate structure includes a high-k dielectric layer on the substrate and a bottom barrier metal (BBM) layer on the high-k dielectric layer. Preferably, the BBM layer includes a top portion, a middle portion, and a bottom portion, in which the top portion being a nitrogen rich portion, and the middle portion and the bottom portion being titanium rich portions.
Abstract translation: 公开了一种半导体器件。 半导体器件包括衬底和衬底上的栅极结构。 栅极结构包括在衬底上的高k电介质层和高k电介质层上的底部阻挡金属(BBM)层。 优选地,BBM层包括顶部,中间部分和底部,其中顶部是富氮部分,中部和底部是富钛部分。
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