公开(公告)号：US08438337B1

公开(公告)日：2013-05-07

申请号：US12571230

申请日：2009-09-30

Applicant: Gaurav Garg ,  David T. Hass

Inventor： Gaurav Garg ,  David T. Hass

IPC: G06F12/00

CPC classification number: G06F12/0815 ,  G06F12/0813 ,  G06F12/0831 ,  G06F12/084 ,  G06F2212/1024 ,  G06F2212/2542

Abstract: A system and method are provided for sharing data between a network including one or more network nodes. The network includes a number of individual network nodes and a home network node communicating with one another. The individual network nodes and the home network node include a plurality of processors and memory caches. The memory caches consist of private caches corresponding to individual processors, as well as shared caches which are shared among the plurality of processors of an individual node and accessible by the processors of the other network nodes. Each network node is capable of executing a hierarchy of data requests that originate in the private caches of an individual local network node. If no cache hits occur within the local network node, a conditional request is sent to the home network node to request data through the shared caches of the other network nodes.

Abstract translation: 提供了一种用于在包括一个或多个网络节点的网络之间共享数据的系统和方法。 网络包括多个单独的网络节点和彼此通信的家庭网络节点。 各个网络节点和家庭网络节点包括多个处理器和存储器高速缓存。 存储器高速缓存由对应于各个处理器的专用高速缓存组成，以及在单个节点的多个处理器之间共享且可由其他网络节点的处理器访问的共享高速缓存。 每个网络节点能够执行源自个别本地网络节点的专用高速缓存中的数据请求的层次。 如果在本地网络节点内没有发生高速缓存命中，则向家庭网络节点发送条件请求，以通过其他网络节点的共享缓存来请求数据。

公开(公告)号：US08433018B2

公开(公告)日：2013-04-30

申请号：US12130732

申请日：2008-05-30

Applicant: Stefanos Sidiropoulos ,  Marc Loinaz ,  R. Sekhar Narayanaswami ,  Nikhil Acharya ,  Dean Liu

Inventor： Stefanos Sidiropoulos ,  Marc Loinaz ,  R. Sekhar Narayanaswami ,  Nikhil Acharya ,  Dean Liu

IPC: H04L7/00

CPC classification number: H03L7/0893 ,  H03K5/133 ,  H03K2005/00052 ,  H03L7/081 ,  H03L7/0895 ,  H03L7/093 ,  H03L7/0998 ,  H03L7/18

Abstract: A frequency synthesis circuit includes a phase locked loop and an interpolator circuit. The phase locked loop circuit receives a reference clock and a feedback clock and generates an output clock with a frequency based on the reference clock and the feedback clock. An interpolator circuit is coupled in the feedback path of the phase locked loop circuit. An interpolator control circuit generates an interpolator control word that specifies a variable time delay for the interpolator circuit. The interpolator circuit receives the output clock, and generates the feedback clock by introducing a variable time delay in the output clock in accordance with the interpolator control word. The time variable delay varies the frequency of the output circuit. Embodiments for frequency synthesis circuits that include a spread spectrum frequency clock generator, frequency modulators, and a fixed frequency clock generator circuit are disclosed.

Abstract translation: 频率合成电路包括锁相环和内插器电路。 锁相环电路接收参考时钟和反馈时钟，并产生基于参考时钟和反馈时钟的频率的输出时钟。 内插器电路耦合在锁相环电路的反馈路径中。 内插器控制电路产生指定内插器电路的可变时间延迟的内插器控制字。 内插器电路接收输出时钟，并根据内插器控制字在输出时钟中引入可变时间延迟来产生反馈时钟。 时间可变延迟会改变输出电路的频率。 公开了包括扩频频率时钟发生器，频率调制器和固定频率时钟发生器电路的频率合成电路的实施例。

公开(公告)号：US08370113B2

公开(公告)日：2013-02-05

申请号：US12152843

申请日：2008-05-16

Applicant: Roy G. Batruni

Inventor： Roy G. Batruni

IPC: H03F1/32 ,  H03F1/12 ,  H03F1/18 ,  H03F1/26

CPC classification number: H04B1/10 ,  G01R31/31709 ,  H03H21/0012 ,  H03H2021/0041 ,  H03H2021/0083 ,  H03M1/1042 ,  H03M1/12

Abstract: A signal processing method includes inputting a digital signal, providing a plurality of coefficients; and determining an output. The output is approximately equal to an aggregate of a plurality of linear reference components, and each of the linear reference components is approximately equal to an aggregate of a corresponding set of digital signal samples that is scaled by the plurality of coefficients.

公开(公告)号：US08369809B2

公开(公告)日：2013-02-05

申请号：US11881821

申请日：2007-07-27

Applicant: Roy G. Batruni

Inventor： Roy G. Batruni

IPC: H04B1/10

CPC classification number: H04B1/0475 ,  H03F1/3223 ,  H03F3/24 ,  H04B2001/0441

Abstract: A device for generating a crest factor reduced signal is disclosed. The device comprises an interface for receiving an input signal; a peak identifier for identifying one or more peak regions of the input signal; a squelch level determiner for determining a reduction of the input signal near the one or more peak regions; a squelcher for reducing the one or more peak regions of the input signal as indicated by the squelch level determiner; and an interface for outputting a crest factor reduced signal. The crest factor reduced signal has a reduced dynamic range due to the reduction of the one or more peak regions of the input signal. The crest factor reduced signal also has been filtered to reduce undesired frequency components by: calculating a difference between a squelched signal from the squelcher and the input signal, band-pass filtering the difference to generate a result, and summing the result with the input signal that has been delayed.

公开(公告)号：US08369121B2

公开(公告)日：2013-02-05

申请号：US13351689

申请日：2012-01-17

Applicant: Carl Gyllenhammer ,  Greg Watson ,  Venkat Gaddam ,  Varadarajan Srinivasan ,  Sandeep Khanna ,  Chetan Deshpande

Inventor： Carl Gyllenhammer ,  Greg Watson ,  Venkat Gaddam ,  Varadarajan Srinivasan ,  Sandeep Khanna ,  Chetan Deshpande

IPC: G11C15/00

CPC classification number: G11C15/04 ,  G11C15/00

Abstract: The power consumption of a search engine such as a CAM device is dynamically adjusted to prevent performance degradation and/or damage resulting from overheating. For some embodiments, the CAM device is continuously sampled to generate sampling signals indicating the number of active states and number of compare operations performed during each sampling period. The sampling signals are accumulated to generate an estimated device power profile, which is compared with reference values corresponding to predetermined power levels to generate a dynamic power control signal indicating predicted increases in the device's operating temperature resulting from its power consumption. The dynamic power control signal is then used to selectively reduce the input data rate of the CAM device, thereby reducing power consumption and allowing the device to cool.

Abstract translation: 动态地调整诸如CAM设备的搜索引擎的功耗以防止由过热导致的性能下降和/或损坏。 对于一些实施例，CAM设备被连续采样以产生指示在每个采样周期期间执行的活动状态数量和比较操作数的采样信号。 累积采样信号以产生估计的设备功率曲线，其与与预定功率水平相对应的参考值进行比较，以产生指示由其功耗引起的设备的工作温度的预测增加的动态功率控制信号。 然后使用动态功率控制信号来选择性地降低CAM设备的输入数据速率，从而降低功耗并允许设备冷却。

公开(公告)号：US08340294B2

公开(公告)日：2012-12-25

申请号：US12008709

申请日：2008-01-10

Applicant: Roy G. Batruni

Inventor： Roy G. Batruni

IPC: H04L9/00

CPC classification number: H04L9/0668 ,  H04K1/00 ,  H04L27/00

Abstract: A system and method are disclosed for securely transmitting and receiving a signal. A nonlinear keying modulator is used in the transmitter to encrypt the signal using a nonlinear keying modulation technique. A nonlinear keying demodulator is used in the receiver to decrypt the signal.

Abstract translation: 公开了用于安全地发送和接收信号的系统和方法。 发射机使用非线性密钥调制器，使用非线性密钥调制技术对信号进行加密。 在接收机中使用非线性键控解调器对信号进行解密。

公开(公告)号：US20120324157A1

公开(公告)日：2012-12-20

申请号：US13330662

申请日：2011-12-19

Applicant: Gaurav Singh ,  Daniel Chen ,  Dave Hass

Inventor： Gaurav Singh ,  Daniel Chen ,  Dave Hass

IPC: G06F12/00

CPC classification number: G06F12/1027 ,  Y02D10/13

Abstract: Extended translation look-aside buffers (eTLB) for converting virtual addresses into physical addresses are presented, the eTLB including, a physical memory address storage having a number of physical addresses, a virtual memory address storage configured to store a number of virtual memory addresses corresponding with the physical addresses, the virtual memory address storage including, a set associative memory structure (SAM), and a content addressable memory (CAM) structure; and comparison circuitry for determining whether a requested address is present in the virtual memory address storage, wherein the eTLB is configured to receive an index register for identifying the SAM structure and the CAM structure, and wherein the eTLB is configured to receive an entry register for providing a virtual page number corresponding with the plurality of virtual memory addresses.

Abstract translation: 呈现用于将虚拟地址转换成物理地址的扩展翻译后备缓冲器（eTLB），eTLB包括具有多个物理地址的物理存储器地址存储器，虚拟存储器地址存储器，被配置为存储对应的多个虚拟存储器地址 物理地址，虚拟存储器地址存储包括集合关联存储器结构（SAM）和内容可寻址存储器（CAM）结构; 以及用于确定所请求的地址是否存在于所述虚拟存储器地址存储器中的比较电路，其中所述eTLB被配置为接收用于识别所述SAM结构和所述CAM结构的索引寄存器，并且其中所述eTLB被配置为接收用于 提供与所述多个虚拟存储器地址对应的虚拟页码。

公开(公告)号：US08331446B2

公开(公告)日：2012-12-11

申请号：US12202293

申请日：2008-08-31

Applicant: Erik M. Schlanger ,  Brendan D. Donahe ,  Eric Swartzendruber ,  Eric J. DeVolder

Inventor： Erik M. Schlanger ,  Brendan D. Donahe ,  Eric Swartzendruber ,  Eric J. DeVolder

IPC: H04N7/12 ,  H04N11/02 ,  H04N11/04 ,  G06F12/02 ,  G06F12/06

CPC classification number: H04N7/32 ,  G11B2020/10537 ,  G11B2020/10759 ,  H04N19/127 ,  H04N19/174 ,  H04N19/42 ,  H04N19/50 ,  H04N19/61

Abstract: A method and device that allow picture slices of a video stream to be processed in an order different than the order they were received is disclosed. Information mapping the location of picture slices that are stored in the order they were received is stored to allow subsequent processing to access the picture slice in any order, including render order.

Abstract translation: 公开了允许视频流的图像片段以与它们被接收的顺序不同的顺序被处理的方法和装置。 存储以其接收的顺序存储的图像片段的位置的信息被存储以允许后续处理以包括渲染顺序的任何顺序访问图像片段。

公开(公告)号：US08324929B1

公开(公告)日：2012-12-04

申请号：US12826124

申请日：2010-06-29

Applicant: Vinay Raja Iyengar ,  Venkat Rajendher Reddy Gaddam ,  Bindiganavale S. Nataraj

Inventor： Vinay Raja Iyengar ,  Venkat Rajendher Reddy Gaddam ,  Bindiganavale S. Nataraj

IPC: H03K19/173 ,  H03K19/00

CPC classification number: H03K19/1732 ,  H03K19/17744

Abstract: An integrated circuit device can include a core section coupled to a plurality of signal paths having a predetermined physical order with respect to one another. A configuration circuit can selectively connect each signal path to a corresponding one of a plurality of physical connection points to the IC device according to one of at least two different physical orders in response to configuration information.

Abstract translation: 集成电路设备可以包括耦合到具有相对于彼此的预定物理顺序的多个信号路径的核心部分。 响应于配置信息，配置电路可以根据至少两个不同的物理顺序中的一个选择性地将每个信号路径连接到多个物理连接点中的对应的一个到IC设备。

公开(公告)号：US08149862B1

公开(公告)日：2012-04-03

申请号：US10452563

申请日：2003-05-30

Applicant: Craig S. Forrest ,  Gaurav Singh ,  Kiran B. Kattel

Inventor： Craig S. Forrest ,  Gaurav Singh ,  Kiran B. Kattel

IPC: H04J3/16

CPC classification number: H04J3/047 ,  H03M9/00 ,  H04J3/0697 ,  H04L12/413

Abstract: A multi-protocol communication circuit, for example, a serializer-deserializer (SerDes) circuit for communicating between an internal logic circuit and an external link includes a select terminal configured to accept a select signal representing a plurality of mode select signal. A SerDes core is coupled to the select terminal and configured to transmit outbound data conforming with a first communication protocol in response to a first mode select signal and conforming with a second communication protocol in response to a second mode select signal. The SerDes core is also configured to receive inbound data respective to a first communication protocol in response to a first mode select signal and respective to a second communication protocol in response to a second mode select signal. Advantages of the invention include the ability to provide high bandwidth communications between integrated circuits that employ different SerDes protocols.

Abstract translation: 多协议通信电路，例如用于在内部逻辑电路和外部链路之间进行通信的串行器 - 解串器（SerDes）电路包括被配置为接受表示多个模式选择信号的选择信号的选择端子。 SerDes核心耦合到选择终端，并且被配置为响应于第一模式选择信号并响应于第二模式选择信号而符合第二通信协议来发送符合第一通信协议的出站数据。 SerDes核还被配置为响应于第一模式选择信号并响应于第二模式选择信号而相应于第二通信协议接收相应于第一通信协议的入站数据。 本发明的优点包括在采用不同SerDes协议的集成电路之间提供高带宽通信的能力。