公开(公告)号：US20020060601A1

公开(公告)日：2002-05-23

申请号：US09542183

申请日：2000-04-04

Inventor： Ali Rastegar

IPC: G05F003/02

CPC classification number: H03F1/56 ,  H03B5/08 ,  H03B2201/0208 ,  H03B2201/025 ,  H03B2201/0266 ,  H03F3/191 ,  H03J1/0008 ,  H03J5/246 ,  H03J2200/10 ,  H03M1/804

Abstract: A structure (110, 150) for enhancing the quality factor (Q) of a capacitive circuit (112, 152). The capacitive circuit (112, 152) includes a first resistance (122, 164), a capacitance (124, 166), and a second resistance (126, 168). The capacitance (124, 166) represents the net capacitance of the capacitive circuit (112, 152), and the first resistance (122, 164) and second resistance (126, 168) represent elements of the intrinsic resistance of the capacitive circuit (112, 152). In a one embodiment the structure (110) includes a first capacitor (128) which is connected in parallel with the capacitive circuit (112), and second capacitor (130) which is connected in series with the capacitive circuit (112). In a second embodiment the structure (150) includes a first inductor (164), connected in series between the capacitive circuit (152) and a node (162) where the first capacitor (174) and one end of the second capacitor (176) connect, and a second inductor (172) connected in series between the capacitive circuit (152) and the other end of the second capacitor (130).

Abstract translation: 一种用于增强电容电路（112,152）的品质因数（Q）的结构（110,150）。 电容电路（112,152）包括第一电阻（122,164），电容（124,166）和第二电阻（126,168）。 电容（124,166）表示电容电路（112,152）的净电容，第一电阻（122,164）和第二电阻（126,168）表示电容电路（112）的固有电阻的元件 ，152）。 在一个实施例中，结构（110）包括与电容电路（112）并联连接的第一电容器（128）和与电容电路（112）串联连接的第二电容器（130）。 在第二实施例中，结构（150）包括串联连接在电容电路（152）和节点（162）之间的第一电感器（164），其中第一电容器（174）和第二电容器（176）的一端 连接，并且串联连接在电容电路（152）和第二电容器（130）的另一端之间的第二电感器（172）。

公开(公告)号：US06356135B1

公开(公告)日：2002-03-12

申请号：US09490599

申请日：2000-01-25

Applicant: Ali Rastegar

Inventor： Ali Rastegar

IPC: G06F718

CPC classification number: H03B5/08 ,  H03B2201/0208 ,  H03B2201/025 ,  H03B2201/0266 ,  H03F3/191 ,  H03J1/0008 ,  H03J2200/10 ,  H03M1/804

Abstract: An electronically trimable capacitor (10) having a plurality of branch circuits (30) each including a capacitor (32) which may be selectively controlled by a switch (34) to contribute or not to the net capacitance exhibited by the trimable capacitor (10). Operation of the switches (34) is under direction of an interface (36), which can receive a program signal containing digital instruction for programming via a program terminal (22). An optional memory (38) permits storing a program of states for the switches (34), so that the interface (36) maybe instructed to reset the switches (34) and thus cause the trimable capacitor (10) again provide a previously programmed net capacitance, say, in the event of power on or a power loss. An optional enable terminal (24) provides protection against inadvertent programming.

Abstract translation: 一种具有多个分支电路（30）的电子可调电容器（10），每个分支电路（30）均包括可由开关（34）选择性地控制的电容器（32），用于对可修整电容器（10）所呈现的净电容作出贡献， 。 开关（34）的操作在接口（36）的方向上，其可以接收包含用于经由程序终端（22）编程的数字指令的程序信号。 可选择的存储器（38）允许存储用于开关（34）的状态程序，使得可以指示接口（36）复位开关（34），并且因此使可修整电容器（10）再次提供预先编程的网络 电容，例如在上电或断电的情况下。 可选的使能端子（24）提供防止无意编程的保护。

公开(公告)号：US06323736B2

公开(公告)日：2001-11-27

申请号：US09824277

申请日：2001-04-02

Applicant: Lars Gustaf Jansson

Inventor： Lars Gustaf Jansson

IPC: H03B512

CPC classification number: H03F3/45085 ,  H01L27/0805 ,  H03B5/1215 ,  H03B5/1231 ,  H03B5/124 ,  H03B5/1265 ,  H03B2201/0266 ,  H03B2201/0283 ,  H03F1/56 ,  H03F2203/45631 ,  H03F2203/45638 ,  H03J2200/10 ,  H03L7/099 ,  H03L7/10 ,  H03L7/18

Abstract: A method and apparatus for digitally controlling the capacitance of an integrated circuit device using MOS-FET devices. In accordance with one aspect of the present invention, a one-bit or “binary” varactor is presented wherein the gate-to-bulk capacitance of the MOS-FET device exhibits dependency to a D.C. voltage applied between its gate and well implant regions. The capacitance-voltage characteristic of the binary capacitor has three major regions: (1) a first relatively flat region having little or no voltage dependency and having a capacitance equal to a first low capacitance of C1; (2) a sloped region wherein a voltage dependency exists; and (3) a second relatively flat region where there is little or no voltage dependency and where the capacitance equals a second higher capacitance of C2. The capacitance of the binary capacitor can be changed from C1 to C2 simply by changing the polarity of the applied D.C. voltage from a positive to a negative value. A plurality of binary capacitors are configured in a parallel arrangement to produce a digitally controlled capacitor. The digitally controlled capacitor can be used in any integrated circuit requiring a tightly controlled tuned network. One application is a voltage-controlled oscillator (VCO) wherein the center output frequency of the VCO is calibrated by digitally modifying the capacitance of the VCO's digitally controlled capacitor. A means for determining whether the VCO requires calibration and a means for calibrating the center output frequency of the VCO is presented.

Abstract translation: 一种使用MOS-FET器件数字控制集成电路器件的电容的方法和装置。 根据本发明的一个方面，提出了一种一位或“二进制”变容二极管，其中MOS-FET器件的栅极 - 体积电容表现出对其栅极和阱注入区域之间施加的直流电压的依赖性。 二元电容器的电容电压特性具有三个主要区域：（1）具有很小或没有电压依赖性并具有等于C1的第一低电容的电容的第一相对平坦的区域; （2）存在电压依赖性的倾斜区域; 和（3）几乎没有或没有电压依赖性并且电容等于C2的第二较高电容的第二相对平坦的区域。 通过将所施加的直流电压的极性从正值改变为负值，可以将二进制电容器的电容从C1改变为C2。 多个二进制电容器被配置成并联布置以产生数字控制的电容器。 数字控制电容器可用于需要严格控制的调谐网络的任何集成电路中。 一种应用是压控振荡器（VCO），其中VCO的中心输出频率通过数字修改VCO的数字控制电容器的电容来校准。 提出了一种用于确定VCO是否需要校准的装置，以及用于校准VCO的中心输出频率的装置。

公开(公告)号：US20010017573A1

公开(公告)日：2001-08-30

申请号：US09754192

申请日：2001-01-05

Applicant: Fox Enterprises, Inc., a Florida Corporation and Jet City Electronic, a Washington Corporation

Inventor： John W. Fallisgaard ,  Eugene S. Trefethan

IPC: H03L007/06 ,  H03L007/16 ,  H03B005/36

CPC classification number: H03L7/183 ,  H03B5/366 ,  H03B19/00 ,  H03B2201/0266 ,  H03J2200/10 ,  H03L7/0898

Abstract: A programmable crystal oscillator is provided having a memory for storing frequency-defining parameters. Typically, one of these parameters is used to program an adjustable capacitive load circuit coupled to a crystal to thereby adjust the crystal source frequency. Additional parameters are used to program the output frequency of a phase locked loop circuit coupled to receive the adjusted source frequency. A further parameter can also be used to divide the output frequency of the phase locked loop circuit to supply a specified output frequency. The oscillators can be manufactured as generic programmable crystal oscillators without regard for output frequency and then quickly programmed to produce customer-specified output frequencies with a high degree of accuracy.

Abstract translation: 提供了一种可编程晶体振荡器，其具有用于存储频率定义参数的存储器。 通常，这些参数之一用于对耦合到晶体的可调容性负载电路进行编程，从而调节晶体源频率。 附加参数用于编程耦合以接收经调整的源频率的锁相环电路的输出频率。 还可以使用另外的参数来分频锁相环电路的输出频率以提供指定的输出频率。 振荡器可以制造为通用可编程晶体振荡器，而不考虑输出频率，然后快速编程，以高精度产生客户指定的输出频率。

公开(公告)号：US06268776B1

公开(公告)日：2001-07-31

申请号：US09434677

申请日：1999-11-05

Applicant: Kevin G. Faison ,  Eric Naviasky ,  Martin J. Mengele

Inventor： Kevin G. Faison ,  Eric Naviasky ,  Martin J. Mengele

IPC: H03B532

CPC classification number: H03B5/364 ,  H03B2201/0266

Abstract: A digitally tuned and linearized low voltage crystal oscillator integrated circuit requires only an oscillator crystal as external circuitry. The inventive circuit operates at voltages of 3.3V and below and requires no other off-chip components. A crystal oscillator, such as a Pierce crystal oscillator uses an inverting gain stage and a phase shift network composed of an array of switchable capacitors and the crystal. The design offers improvements in power consumption, area, manufacturability and cost.

Abstract translation: 数字调谐和线性化的低压晶体振荡器集成电路只需要一个振荡器晶体作为外部电路。 本发明电路在3.3V及以下的电压下工作，不需要其它芯片外部件。 诸如皮尔斯晶体振荡器的晶体振荡器使用由可切换电容器和晶体阵列组成的反相增益级和相移网络。 该设计提供了功耗，面积，可制造性和成本的改进。

公开(公告)号：US5952890A

公开(公告)日：1999-09-14

申请号：US795978

申请日：1997-02-05

Applicant: John W. Fallisgaard ,  Eugene S. Trefethan

Inventor： John W. Fallisgaard ,  Eugene S. Trefethan

IPC: H03B5/32 ,  H03B1/00 ,  H03B5/36 ,  H03B19/00 ,  H03L7/089 ,  H03L7/18 ,  H03L7/183 ,  H03L7/06

CPC classification number: H03L7/183 ,  H03B19/00 ,  H03B5/366 ,  H03B2201/0266 ,  H03J2200/10 ,  H03L7/0898

Abstract: A programmable crystal oscillator is provided having a memory for storing frequency-defining parameters. Typically, one of these parameters is used to program an adjustable capacitive load circuit coupled to a crystal to thereby adjust the crystal source frequency. Additional parameters are used to program the output frequency of a phase locked loop circuit coupled to receive the adjusted source frequency. A further parameter can also be used to divide the output frequency of the phase locked loop circuit to supply a specified output frequency. The oscillators can be manufactured as generic programmable crystal oscillators without regard for output frequency and then quickly programmed to produce customer-specified output frequencies with a high degree of accuracy.

Abstract translation: 提供了一种可编程晶体振荡器，其具有用于存储频率定义参数的存储器。 通常，这些参数之一用于对耦合到晶体的可调容性负载电路进行编程，从而调节晶体源频率。 附加参数用于编程耦合以接收经调整的源频率的锁相环电路的输出频率。 还可以使用另外的参数来分频锁相环电路的输出频率以提供指定的输出频率。 振荡器可以制造为通用可编程晶体振荡器，而不考虑输出频率，然后快速编程，以高精度产生客户指定的输出频率。

公开(公告)号：US5614870A

公开(公告)日：1997-03-25

申请号：US530346

申请日：1995-09-28

Applicant: Donald J. Sauer ,  William E. Rodda ,  Edward R. Campbell, III

Inventor： Donald J. Sauer ,  William E. Rodda ,  Edward R. Campbell, III

IPC: H03B1/00 ,  H03L7/099 ,  H03L7/113 ,  H03L7/14 ,  H04N7/12 ,  H03L7/087

CPC classification number: H04N7/122 ,  H03L7/0991 ,  H03L7/113 ,  H03L7/14 ,  H03B2201/02 ,  H03B2201/0266 ,  H03J2200/10

Abstract: A frequency detector of a phase-lock-loop circuit is used for measuring a frequency error between a frequency of an output signal of an oscillator and a frequency of a synchronizing signal. When the frequency error in each of 32 periods of the synchronizing signal exceeds a predetermined magnitude, the phase-lock-loop circuits begins operating in a coarse frequency correction mode. As long as the 32 periods have not lapsed, the phase-lock-loop circuit operates in an idle mode of operation and the oscillator is not corrected. As a result, during vertical retrace, when equalizing pulses occur, the phase-lock-loop circuit is not disturbed by a large frequency error.

Abstract translation: PCT No.PCT / US94 / 04304 Sec。 371 1995年9月28日第 102（e）1995年9月28日PCT PCT 1994年4月19日PCT公布。 公开号WO94 / 26041 日期：1994年11月10日使用锁相环电路的频率检测器来测量振荡器的输出信号的频率和同步信号的频率之间的频率误差。 当同步信号的32个周期中的每个周期中的频率误差超过预定幅度时，锁相环电路以粗频率校正模式开始工作。 只要32个周期没有经过，锁相环电路就工作在空闲的工作模式，并且振荡器不被校正。 结果，在垂直回扫期间，当产生均衡脉冲时，锁相环电路不会受到大的频率误差的干扰。

公开(公告)号：US5610560A

公开(公告)日：1997-03-11

申请号：US525684

申请日：1995-12-11

Applicant: Donald J. Sauer ,  William E. Rodda ,  Edward R. Campbell, III

Inventor： Donald J. Sauer ,  William E. Rodda ,  Edward R. Campbell, III

IPC: H03B1/00 ,  H03L7/099 ,  H03L7/113 ,  H03L7/14 ,  H04N7/12 ,  H03B5/24

CPC classification number: H04N7/122 ,  H03L7/0991 ,  H03L7/113 ,  H03L7/14 ,  H03B2201/02 ,  H03B2201/0266 ,  H03J2200/10

Abstract: A phase-locked-loop circuit includes an oscillator having switched capacitors that are selectively coupled to a positive feedback path of the oscillator in a coarse frequency error correction mode of operation. When the frequency error is small, the circuit operates in a fine error correction mode without varying the selection of the switched reactive elements.

Abstract translation: PCT No.PCT / US94 / 04404 Sec。 371 1995年12月11日第 102（e）日期1995年12月11日PCT 1994年4月19日PCT PCT。 WO94 / 24767 PCT出版物 日期：1994年10月27日一种锁相环电路包括具有开关电容器的振荡器，其以粗频率误差校正操作模式选择性地耦合到振荡器的正反馈路径。 当频率误差小时，电路在精细的误差校正模式下工作，而不改变切换的无功元件的选择。

公开(公告)号：US3614665A

公开(公告)日：1971-10-19

申请号：US3614665D

申请日：1970-04-06

Applicant: AVCO CORP

Inventor： WELLER CARROLL E ,  MCNAIR ROBERT J

IPC: H03B1/00 ,  H03B5/12 ,  H03B5/18 ,  H03L7/187

CPC classification number: H03L7/187 ,  H03B5/1203 ,  H03B5/1228 ,  H03B5/1243 ,  H03B5/1265 ,  H03B5/1805 ,  H03B2201/0208 ,  H03B2201/0266 ,  H03J2200/10

Abstract: This is a voltage-controlled oscillator. The tank circuit of the oscillator comprises a plurality of capacitors, the capacitance magnitudes of which are related to each other in binary fashion. Also incorporated in this tank circuit is a voltage variable capacitor, to which a bias is applied for tuning purposes. By programmed switching one or more of the aforementioned capacitances are switched into the tank circuit, so as to bring the oscillator within the pull-in range of a phase lock loop. The elements of the oscillator are related to a coaxial line structure. The invention further provides a convenient mounting on which the tank circuit parameters are arranged. The various lumped capacitances in the tank circuit are switched in and out by PIN diodes.