利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

23 条记录 (耗时 0.021 秒)

    Process sequence for doped silicon fill of deep trenches
    11.
    发明申请
    Process sequence for doped silicon fill of deep trenches 有权

    公开(公告)号：US20060128139A1

    公开(公告)日：2006-06-15

    申请号：US11011550

    申请日：2004-12-14

    申请人： Ajit Paranjpe ,  Somnath Nag

    发明人： Ajit Paranjpe ,  Somnath Nag

    IPC分类号： H01L21/4763

    CPC分类号： C23C16/045 ,  C23C16/24 ,  H01L21/76232 ,  H01L29/66181

    摘要： A method for void free filling with in-situ doped amorphous silicon of a deep trench structure is provided in which a first fill is carried out in at a temperature, pressure and dopant to silane ratio such that film deposition occurs from the bottom of the trench upwards. By way of this first fill, step coverages well in excess 100% are achieved. In the second fill step, deposition is carried out under changed conditions so as to reduce the impact of dopant on deposition rate, whereby trench fill is completed at a deposition rate which exceeds the deposition rate of the first fill. In an application of this method to the formation of deep trench capacitor structures, the intermediate steps further including the capping of the void free filled trench with a thick layer of amorphous silicon, planarization of the wafer thereafter, followed by a thermal anneal to re-distribute the dopant within the filled trench. Thereafter, additional steps can be performed to complete the formation of the capacitor structure.

    Sectional wafer carrier
    13.
    发明授权
    Sectional wafer carrier 失效
    截面晶圆载体

    公开(公告)号：US08562746B2

    公开(公告)日：2013-10-22

    申请号：US12968900

    申请日：2010-12-15

    申请人： Alexander I. Gurary ,  Joseph Arthur Kraus ,  Ajit Paranjpe ,  William E. Quinn ,  David Albert Crewe

    发明人： Alexander I. Gurary ,  Joseph Arthur Kraus ,  Ajit Paranjpe ,  William E. Quinn ,  David Albert Crewe

    IPC分类号： C23C16/00 ,  C23F1/00 ,  H01L21/306

    CPC分类号： C23C16/4584 ,  C23C16/4585 ,  C23C16/4586 ,  H01L21/67754 ,  H01L21/68707 ,  H01L21/6875 ,  H01L21/68764 ,  H01L21/68771

    摘要： A structure for a chemical vapor deposition reactor includes a support element defining oppositely-facing substantially planar upper and lower surfaces and a vertical rotational axis substantially perpendicular to the upper and lower surfaces, and a plurality of carrier sections releasably engaged with the support element. Each carrier section can include oppositely-facing substantially planar top and bottom surfaces and at least one aperture extending between the top and bottom surfaces. The carrier sections can be disposed on the support element with the bottom surfaces of the carrier sections facing toward the upper surface of the support element, so that wafers can be held in the apertures of the carrier sections with one surface of each wafer confronting the support element and an opposite surface exposed at the top surface of the carrier sections.

    摘要翻译： 用于化学气相沉积反应器的结构包括限定相对面对的基本平坦的上表面和下表面的支撑元件和基本上垂直于上表面和下表面的垂直旋转轴线，以及与支撑元件可释放地接合的多个承载部件。 每个载体部分可以包括相对面对的基本平坦的顶部和底部表面以及在顶部和底部表面之间延伸的至少一个孔。 载体部分可以设置在支撑元件上，其中承载部分的底表面朝向支撑元件的上表面，使得晶片可以保持在载体部分的孔中，每个晶片的一个表面面对支撑件 元件和暴露在载体部分的顶表面处的相对表面。

    SECTIONAL WAFER CARRIER
    16.
    发明申请
    SECTIONAL WAFER CARRIER 失效

    公开(公告)号：US20120156374A1

    公开(公告)日：2012-06-21

    申请号：US12968900

    申请日：2010-12-15

    申请人： Alexander I. Gurary ,  Joseph Arthur Kraus ,  Ajit Paranjpe ,  William E. Quinn ,  David Albert Crewe

    发明人： Alexander I. Gurary ,  Joseph Arthur Kraus ,  Ajit Paranjpe ,  William E. Quinn ,  David Albert Crewe

    IPC分类号： C23C16/458 ,  C23C16/46

    CPC分类号： C23C16/4584 ,  C23C16/4585 ,  C23C16/4586 ,  H01L21/67754 ,  H01L21/68707 ,  H01L21/6875 ,  H01L21/68764 ,  H01L21/68771

    摘要： A structure for a chemical vapor deposition reactor includes a support element defining oppositely-facing substantially planar upper and lower surfaces and a vertical rotational axis substantially perpendicular to the upper and lower surfaces, and a plurality of carrier sections releasably engaged with the support element. Each carrier section can include oppositely-facing substantially planar top and bottom surfaces and at least one aperture extending between the top and bottom surfaces. The carrier sections can be disposed on the support element with the bottom surfaces of the carrier sections facing toward the upper surface of the support element, so that wafers can be held in the apertures of the carrier sections with one surface of each wafer confronting the support element and an opposite surface exposed at the top surface of the carrier sections.

    摘要翻译： 用于化学气相沉积反应器的结构包括限定相对面对的基本平坦的上表面和下表面的支撑元件和基本上垂直于上表面和下表面的垂直旋转轴线，以及与支撑元件可释放地接合的多个承载部件。 每个载体部分可以包括相对面对的基本平坦的顶部和底部表面以及在顶部和底部表面之间延伸的至少一个孔。 载体部分可以设置在支撑元件上，其中承载部分的底表面朝向支撑元件的上表面，使得晶片可以保持在载体部分的孔中，每个晶片的一个表面面对支撑件 元件和暴露在载体部分的顶表面处的相对表面。

    Process sequence for doped silicon fill of deep trenches
    17.
    发明授权
    Process sequence for doped silicon fill of deep trenches 有权
    深沟槽掺杂硅填充工艺顺序

    公开(公告)号：US07713881B2

    公开(公告)日：2010-05-11

    申请号：US12199402

    申请日：2008-08-27

    申请人： Ajit Paranjpe ,  Somnath Nag

    发明人： Ajit Paranjpe ,  Somnath Nag

    IPC分类号： H01L21/311

    CPC分类号： C23C16/045 ,  C23C16/24 ,  H01L21/76232 ,  H01L29/66181

    摘要： A method for void free filling with in-situ doped amorphous silicon of a deep trench structure is provided in which a first fill is carried out in a way so that film deposition occurs from the bottom of the trench upwards, with step coverage well in excess of 100%. In a second fill step, deposition conditions are changed to reduce the impact of dopant on deposition rate, and deposition proceeds at a rate which exceeds the deposition rate of the first fill. In an application of this method to the formation of deep trench capacitor structures, the intermediate steps further including the capping of the void free filled trench with a thick layer of amorphous silicon, planarization of the wafer thereafter, followed by a thermal anneal to re-distribute the dopant within the filled trench. Thereafter, additional steps can be performed to complete the formation of the capacitor structure.

    摘要翻译： 提供了一种用于无缝填充深沟槽结构的原位掺杂非晶硅的方法，其中第一填充以使得膜沉积从沟槽底部向上发生的方式进行，其中步骤覆盖良好地超过 100％。 在第二填充步骤中，改变沉积条件以减少掺杂剂对沉积速率的影响，并且沉积以超过第一填充的沉积速率的速率进行。 在这种方法应用于深沟槽电容器结构的形成中，中间步骤进一步包括无孔填充沟槽的覆盖，其中厚层非晶硅，之后对晶片进行平面化，随后进行热退火， 在填充的沟槽内分布掺杂剂。 此后，可以执行附加步骤以完成电容器结构的形成。

    Poly-silicon-germanium gate stack and method for forming the same
    18.
    发明授权
    Poly-silicon-germanium gate stack and method for forming the same 失效
    聚硅锗栅堆叠及其形成方法

    公开(公告)号：US07354848B2

    公开(公告)日：2008-04-08

    申请号：US11420940

    申请日：2006-05-30

    申请人： Ajit Paranjpe ,  Kangzhan Zhang

    发明人： Ajit Paranjpe ,  Kangzhan Zhang

    IPC分类号： H01L21/3205

    CPC分类号： H01L21/28044 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02505 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/28282 ,  H01L21/823828 ,  H01L29/4925 ,  H01L29/513

    摘要： A CMOS gate stack that increases the inversion capacitance compared to a conventional CMOS gate stack has been described. Using a poly-SiGe gate, instead of the conventional poly-Si gate near the gate dielectric layer, increases the amount of implanted dopant that can be activated. This increase overcomes the polysilicon depletion problem that limits the inversion capacitance in the conventional CMOS gate stack. To integrate the poly-SiGe layer into the gate stack, a thin α-Si layer is deposited between the gate dielectric layer and the poly-SiGe layer. To ensure proper salicide formation, a poly-Si layer is capped over the poly-SiGe layer. In order to obtain a fined-grained poly-Si over poly-SiGe, a second α-Si layer is deposited between the poly-Si layer and the poly-SiGe layer.

    摘要翻译： 已经描述了与常规CMOS栅极堆叠相比增加反转电容的CMOS栅极堆叠。 使用多晶硅栅极，代替栅极电介质层附近的常规多晶硅栅极，增加了可被激活的注入掺杂剂的量。 这种增加克服了限制常规CMOS栅极堆叠中的反相电容的多晶硅耗尽问题。 为了将多晶硅层整合到栅极堆叠中，在栅极介电层和多晶硅层之间沉积薄的α-Si层。 为了确保适当的自对准硅化物形成，多晶硅层被覆盖在多晶硅层上。 为了获得多晶SiGe上的细晶粒多晶硅，在多晶硅层和多晶硅层之间沉积第二个α-Si层。

    PROCESS SEQUENCE FOR DOPED SILICON FILL OF DEEP TRENCHES
    19.
    发明申请
    PROCESS SEQUENCE FOR DOPED SILICON FILL OF DEEP TRENCHES 有权
    DEEP TRENCHES DOPED SILICON FILL的工艺顺序

    公开(公告)号：US20060234470A1

    公开(公告)日：2006-10-19

    申请号：US11420893

    申请日：2006-05-30

    申请人： Ajit Paranjpe ,  Somnath Nag

    发明人： Ajit Paranjpe ,  Somnath Nag

    IPC分类号： H01L21/76

    CPC分类号： C23C16/045 ,  C23C16/24 ,  H01L21/76232 ,  H01L29/66181

    摘要： A method for void free filling with in-situ doped amorphous silicon of a deep trench structure is provided in which a first fill is carried out in at a temperature, pressure and dopant to silane ratio such that film deposition occurs from the bottom of the trench upwards. By way of this first fill, step coverages well in excess 100% are achieved. In the second fill step, deposition is carried out under changed conditions so as to reduce the impact of dopant on deposition rate, whereby trench fill is completed at a deposition rate which exceeds the deposition rate of the first fill. In an application of this method to the formation of deep trench capacitor structures, the intermediate steps further including the capping of the void free filled trench with a thick layer of amorphous silicon, planarization of the wafer thereafter, followed by a thermal anneal to re-distribute the dopant within the filled trench. Thereafter, additional steps can be performed to complete the formation of the capacitor structure.

    摘要翻译： 提供了一种无空隙填充深沟槽结构的原位掺杂非晶硅的方法，其中在硅烷比例的温度，压力和掺杂剂下进行第一次填充，使得从沉积的底部发生膜沉积 向上。 通过这个第一次填充，达到100％以上的步骤覆盖率。 在第二填充步骤中，在改变的条件下进行沉积，以减少掺杂剂对沉积速率的影响，由此以超过第一填充物的沉积速率的沉积速率完成沟槽填充。 在这种方法应用于深沟槽电容器结构的形成中，中间步骤进一步包括无孔填充沟槽的覆盖，其中厚层非晶硅，之后对晶片进行平面化，随后进行热退火， 在填充的沟槽内分布掺杂剂。 此后，可以执行附加步骤以完成电容器结构的形成。