公开(公告)号：US06754856B2

公开(公告)日：2004-06-22

申请号：US09748762

申请日：2000-12-22

申请人： Andrew Cofler ,  Isabelle Sename ,  Bruno Bernard

发明人： Andrew Cofler ,  Isabelle Sename ,  Bruno Bernard

IPC分类号： G06F1100

CPC分类号： G06F9/3865 ,  G06F9/30072

摘要： A computer system includes instruction fetch circuitry for dispatching fetched instructions to a pipelined execution unit, data memory access circuitry and emulator circuitry for use in debug operations, said emulator circuitry including error indicating circuitry to indicate an error in a data memory access operation, snoop circuitry for snooping memory access operation in said data memory access circuitry, synchronising means for synchronising snooped data memory access addresses with respective program counts for the instructions associated with said access addresses, memory mapped storage circuitry responsive to a data memory access error to indicate the data memory address associated with the error, whereby the emulator circuitry may use the data memory address in a subsequent operation to obtain from the synchronising means the specific program count associated with the memory access operation in which the error occurred.

摘要翻译： 计算机系统包括指令提取电路，用于将读取的指令分派到流水线执行单元，用于调试操作的数据存储器访问电路和仿真器电路，所述仿真器电路包括用于指示数据存储器访问操作中的错误的错误指示电路，窥探电路 用于在所述数据存储器访问电路中窥探存储器访问操作;同步装置，用于将窥探数据存储器访问地址与用于与所述访问地址相关联的指令的相应程序计数同步;存储器映射存储电路，响应于数据存储器访问错误以指示数据存储器 与模拟器电路相关联的地址，由此仿真器电路可以在随后的操作中使用数据存储器地址，以从同步装置获得与发生错误的存储器访问操作相关联的特定程序计数。

公开(公告)号：US5327031A

公开(公告)日：1994-07-05

申请号：US47545

申请日：1993-03-08

申请人： Roland Marbot ,  Andrew Cofler ,  Michel Combes ,  Jean-Claude Lebihan ,  Reza Nezamzadeh-Moosavi

发明人： Roland Marbot ,  Andrew Cofler ,  Michel Combes ,  Jean-Claude Lebihan ,  Reza Nezamzadeh-Moosavi

IPC分类号： H03K5/00 ,  H03K5/13

CPC分类号： H03K5/133 ,  H03K2005/00039 ,  H03K2005/00065 ,  H03K2005/00195

摘要： A variable delay circuit including a fixed delay circuit (D1) furnishing a signal (e.sub.1) that is delayed with respect to the input signal (e.sub.0). A combination circuit (C) furnishes a combination signal (f.sub.K) resulting from the superposition, with weighting and an integral effect of the input (e.sub.0) and delayed (e.sub.1) signals. The assembly is dimensioned such that the fixed delay (T) is less than the transition time that the combination signal (f.sub.K) has when only the input signal (e.sub.0) is applied.

摘要翻译： 一种可变延迟电路，包括提供相对于输入信号（e0）被延迟的信号（e1）的固定延迟电路（D1）。 组合电路（C）提供由叠加产生的组合信号（fK）与加权和输入（e0）和延迟（e1）信号的积分效应。 组件的尺寸使得固定延迟（T）小于当仅施加输入信号（e0）时组合信号（fK）具有的转变时间。

公开(公告)号：US07486582B2

公开(公告)日：2009-02-03

申请号：US11346796

申请日：2006-02-03

申请人： François Druilhe ,  Andrew Cofler ,  Denis Dutoit ,  Michel Harrand ,  Gilles Eyzat ,  Christian Freund

发明人： François Druilhe ,  Andrew Cofler ,  Denis Dutoit ,  Michel Harrand ,  Gilles Eyzat ,  Christian Freund

IPC分类号： G11C7/00

CPC分类号： G11C11/406 ,  G11C2211/4061 ,  G11C2211/4067

摘要： A DRAM and its application to a mobile telephony circuit with a control circuit including a first refreshment controller controlled by a first clock signal and a second refreshment controller controlled by a second clock signal having a frequency less than that of the first one and used to synchronize events of the GSM network.

摘要翻译： 一种DRAM及其在具有控制电路的移动电话电路中的应用，该控制电路包括由第一时钟信号控制的第一更新控制器和由具有小于第一时钟信号频率的第二时钟信号控制的第二更新控制器，并且用于同步 GSM网络的事件。

公开(公告)号：US07281119B1

公开(公告)日：2007-10-09

申请号：US09563154

申请日：2000-05-02

申请人： Andrew Cofler ,  Bruno Fel ,  Laurent Ducousso

发明人： Andrew Cofler ,  Bruno Fel ,  Laurent Ducousso

IPC分类号： G06F9/00

CPC分类号： G06F9/3836 ,  G06F9/3838 ,  G06F9/3853 ,  G06F9/3857 ,  G06F9/3885

摘要： A computer system supplies instructions simultaneously to a plurality of parallel execution pipelines in either superscalar mode or very long instruction word mode with checks for vertical and horizontal dependency between instructions, the horizontal dependency checks between instructions supplied in the same machine cycle being effective in superscalar mode but disabled in very long instruction word mode.

摘要翻译： 计算机系统以超标量模式或非常长的指令字模式同时向多个并行执行流水线提供指令，同时检查指令之间的垂直和水平相关性，在同一机器周期中提供的指令之间的水平依赖性检查在超标量模式下有效 但在非常长的指令字模式下禁用。

公开(公告)号：US20070174714A1

公开(公告)日：2007-07-26

申请号：US11567990

申请日：2006-12-07

申请人： Renaud Ayrignac ,  Isabelle Sename ,  Andrew Cofler

发明人： Renaud Ayrignac ,  Isabelle Sename ,  Andrew Cofler

IPC分类号： G06F11/00

CPC分类号： G06F11/3656

摘要： A method for debugging a multitask program executed by a processor includes interrupting the processor during the execution of a task of the program, and activating a debugging mode of the processor, wherein the instructions executed by the processor are supplied by an external emulator. The method comprises steps during which: the processor sends an activation message to the external emulator every time the debugging mode is activated, and upon receiving the activation message, the external emulator sends an acknowledgement message to the processor containing at least one portion of the activation message received.

摘要翻译： 用于调试由处理器执行的多任务程序的方法包括在执行程序的任务期间中断处理器，以及激活处理器的调试模式，其中由处理器执行的指令由外部仿真器提供。 该方法包括以下步骤：在每次调试模式被激活时，处理器向外部仿真器发送激活消息，并且在接收到激活消息时，外部仿真器向处理器发送包含至少一部分激活的确认消息 收到消息。

公开(公告)号：US20050010724A1

公开(公告)日：2005-01-13

申请号：US10874804

申请日：2004-06-23

申请人： Andrew Cofler

发明人： Andrew Cofler

IPC分类号： G06F12/08 ,  G06F12/12

CPC分类号： G06F12/126 ,  G06F12/0864

摘要： A cache memory is of the direct access type or of the set-associative type and includes NS sets each containing NW cache lines. NS is an integer greater than one, and NW is an integer equal to or greater than one. In the presence of a cache line access request, the content of the cache memory is scanned, the cache line is accessed if the latter is already allocated, and a new cache line is allocated in the cache memory in the contrary case. The cache memory is subdivided into SB subdivisions. Each subdivision includes NS/SB sub-sets each containing NW cache lines. Each subdivision is assigned a protection indication representative of whether or not the subdivision is protected. The scanning is carried out in all the subdivisions, whether protected or not. The access to a cache line already allocated is carried out even if that cache line belongs to a protected subdivision, whereas the allocation of a new cache line is carried out only in an unprotected subdivision.

摘要翻译： 缓存存储器是直接访问类型或集合关联类型，并且包括每个包含NW个高速缓存行的NS集合。 NS是大于1的整数，NW是等于或大于1的整数。 在存在高速缓存行访问请求的情况下，扫描高速缓冲存储器的内容，如果后者已被分配，则高速缓存行被访问，并且在相反的情况下在高速缓冲存储器中分配新的高速缓存行。 缓存存储器被细分为SB子细分。 每个细分包括每个包含NW高速缓存行的NS / SB子集。 每个细分都被分配一个保护指示，代表分区是否被保护。 扫描是在所有细分中进行的，无论是否受保护。 即使该高速缓存行属于受保护的细分，也可以执行已经分配的高速缓存行的访问，而仅在未受保护的细分中执行新的高速缓存行的分配。

公开(公告)号：US06732276B1

公开(公告)日：2004-05-04

申请号：US09563468

申请日：2000-05-02

申请人： Andrew Cofler ,  Bruno Fel ,  Laurent Ducousso

发明人： Andrew Cofler ,  Bruno Fel ,  Laurent Ducousso

IPC分类号： G06F1700

CPC分类号： G06F9/3838 ,  G06F9/30072 ,  G06F9/3013

摘要： A computer system has a plurality of parallel execution units for executing instructions with assigned guard indicators, one execution unit including a master guard value store and another execution unit having a shadow guard value store, together with guard ownership circuitry to indicate whether the shadow guard value store owns the current value of the guard indicator and transfer circuitry operable to transfer a guard value from the master store to another execution unit.

摘要翻译： 计算机系统具有多个并行执行单元，用于执行具有分配保护指示符的指令，包括主保护值存储器的一个执行单元和具有影子保护值存储器的另一个执行单元，以及保护所有权电路，以指示阴影保护值是否 存储器具有保护指示器的当前值和可操作以将保护值从主存储传送到另一个执行单元的传输电路。

公开(公告)号：US06678818B1

公开(公告)日：2004-01-13

申请号：US09562715

申请日：2000-05-02

申请人： Andrew Cofler ,  Stéphane Bouvier ,  Laurent Wojcieszak

发明人： Andrew Cofler ,  Stéphane Bouvier ,  Laurent Wojcieszak

IPC分类号： G06F930

CPC分类号： G06F9/3822 ,  G06F9/30149 ,  G06F9/30181 ,  G06F9/30189 ,  G06F9/3802 ,  G06F9/3814 ,  G06F9/3885

摘要： A decode unit (20) decodes instructions in a processor. These, instructions include instructions of a first length in a first instruction mode and instructions of a second, shorter length in a second instruction mode. The decode unit has decoding circuitry (50-60) which decode the instructions. A register holds the instruction mode and generates an instruction mode signal. Switching circuitry (MUX6,MUX7) is responsive to the instruction mode signal to output decoded instructions from the decode unit depending on the instruction mode. A detector (70) is provided for detecting a length change instruction of the second, shorter length while in the second instruction mode which indicates that the subsequent instruction is of the first length. The detector also temporarily alters the state of the instruction mode signal to allow the first length instructions to be decoded without changing the instruction mode held in the register.

摘要翻译： 解码单元（20）解码处理器中的指令。 这些指令包括在第一指令模式下具有第一长度的指令和在第二指令模式中的第二较短长度的指令。 解码单元具有对指令进行解码的解码电路（50-60）。 寄存器保持指令模式并产生指令模式信号。 开关电路（MUX6，MUX7）响应于指令模式信号，以根据指令模式从解码单元输出解码指令。 提供检测器（70），用于在第二指令模式中检测第二较短长度的长度变化指令，其指示后续指令是第一长度。 检测器还临时改变指令模式信号的状态，以允许第一长度指令被解码而不改变保持在寄存器中的指令模式。

公开(公告)号：US5614841A

公开(公告)日：1997-03-25

申请号：US362892

申请日：1994-12-23

申请人： Roland Marbot ,  Jean-Claude Le Bihan ,  Andrew Cofler ,  Reza Nezamzadeh-Moosavi

发明人： Roland Marbot ,  Jean-Claude Le Bihan ,  Andrew Cofler ,  Reza Nezamzadeh-Moosavi

IPC分类号： H01L21/8234 ,  H01L27/088 ,  H03K5/00 ,  H03K19/21

CPC分类号： H03K19/215 ,  H03K5/00006

摘要： The gates (11) of the exclusive OR type having two inputs (A, B) are disposed in tree structure in successive layers of an integrated circuit beginning with an input layer which receives the input signals of the tree. The output of each gate is connected to an input of a gate in the adjacent layer. Each gate includes two cells (11a, 11b) that switch substantially simultaneously in response to two respective complementary signals (A, NA; B, NB) from one of the two inputs and that supply respective output signals that are representative of the complementary functions (XOR, NXOR) of the exclusive OR type. This makes it possible to obtain propagation times that are perfectly equal whatever the active input of the tree or the edge to be propagation times that are perfectly equal whatever the active input of the tree or the edge to be propagated may be.

摘要翻译： 具有两个输入（A，B）的异或类型的门（11）以树形结构设置在从接收树的输入信号的输入层开始的集成电路的连续层中。 每个栅极的输出端连接到相邻层中的栅极的输入端。 每个门包括两个单元（11a，11b），其响应于来自两个输入中的一个的两个相应的互补信号（A，NA; B，NB）而基本同时地切换，并提供表示互补功能的各个输出信号 XOR，NXOR）的OR类型。 这使得可以获得完全相等的传播时间，无论树的活动输入或要传播的边缘的传播时间完全相等，无论树的活动输入或要传播的边缘可以是什么。

公开(公告)号：US07685470B2

公开(公告)日：2010-03-23

申请号：US11567990

申请日：2006-12-07

申请人： Renaud Ayrignac ,  Isabelle Sename ,  Andrew Cofler

发明人： Renaud Ayrignac ,  Isabelle Sename ,  Andrew Cofler

IPC分类号： G06F11/00

CPC分类号： G06F11/3656

摘要： A method for debugging a multitask program executed by a processor includes interrupting the processor during the execution of a task of the program, and activating a debugging mode of the processor, wherein the instructions executed by the processor are supplied by an external emulator. The method comprises steps during which: the processor sends an activation message to the external emulator every time the debugging mode is activated, and upon receiving the activation message, the external emulator sends an acknowledgement message to the processor containing at least one portion of the activation message received.

摘要翻译： 用于调试由处理器执行的多任务程序的方法包括在执行程序的任务期间中断处理器，以及激活处理器的调试模式，其中由处理器执行的指令由外部仿真器提供。 该方法包括以下步骤：在每次调试模式被激活时，处理器向外部仿真器发送激活消息，并且在接收到激活消息时，外部仿真器向处理器发送包含至少一部分激活的确认消息 收到消息。