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    Shallow trench isolation structure with low trench parasitic capacitance
    13.
    发明授权
    Shallow trench isolation structure with low trench parasitic capacitance 失效
    浅沟槽隔离结构具有低沟槽寄生电容

    公开(公告)号：US07619294B1

    公开(公告)日：2009-11-17

    申请号：US11262173

    申请日：2005-10-28

    Applicant: Venkatesh P. Gopinath ,  Arvind Kamath ,  Mohammad R. Mirabedini ,  Ming-Yi Lee

    Inventor： Venkatesh P. Gopinath ,  Arvind Kamath ,  Mohammad R. Mirabedini ,  Ming-Yi Lee

    IPC: H01L21/76

    CPC classification number: H01L21/76224

    Abstract: Provided are methods and composition for forming an isolation structure on an integrated circuit substrate. First, a trench is etched in the integrated circuit substrate. A lower dielectric layer is then formed in the trench such that the lower dielectric layer at least partially fills the trench. An upper dielectric layer is then formed over the lower dielectric layer to create an isolation structure, the upper dielectric layer and the lower dielectric layer together having an effective dielectric constant that is less than that of silicon dioxide, thereby enabling capacitance associated with the isolation structure to be reduced.

    Abstract translation: 提供了用于在集成电路基板上形成隔离结构的方法和组合物。 首先，在集成电路基板中蚀刻沟槽。 然后在沟槽中形成下介电层，使得下电介质层至少部分地填充沟槽。 然后在下介电层上形成上电介质层以产生隔离结构，上电介质层和下电介质层一起具有小于二氧化硅的有效介电常数，从而实现与隔离结构相关联的电容 要减少

    Profile Engineered Thin Film Devices and Structures
    14.
    发明申请
    Profile Engineered Thin Film Devices and Structures 有权
    简介工程薄膜器件和结构

    公开(公告)号：US20090085095A1

    公开(公告)日：2009-04-02

    申请号：US12243880

    申请日：2008-10-01

    Applicant: Arvind KAMATH ,  Erik SCHER ,  Patrick SMITH ,  Aditi CHANDRA ,  Steven MOLESA

    Inventor： Arvind KAMATH ,  Erik SCHER ,  Patrick SMITH ,  Aditi CHANDRA ,  Steven MOLESA

    IPC: H01L29/788 ,  H01L29/786 ,  H01L29/00 ,  H01L21/208

    CPC classification number: H01L21/36 ,  C23C18/08 ,  C23C18/122 ,  C23C18/1245 ,  C23C18/1295 ,  H01L21/02532 ,  H01L21/02601 ,  H01L21/02628 ,  H01L21/28273 ,  H01L21/28518 ,  H01L21/288 ,  H01L21/76871 ,  H01L21/76895 ,  H01L27/1285 ,  H01L27/1292 ,  H01L28/40 ,  H01L29/0657 ,  H01L29/66143 ,  H01L29/6675 ,  H01L29/7881 ,  H01L29/872 ,  H05K1/16 ,  H05K1/162 ,  H05K3/125 ,  H05K2201/098

    Abstract: The present invention relates to electrically active devices (e.g., capacitors, transistors, diodes, floating gate memory cells, etc.) having dielectric, conductor, and/or semiconductor layers with smooth and/or dome-shaped profiles and methods of forming such devices by depositing or printing (e.g., inkjet printing) an ink composition that includes a semiconductor, metal, or dielectric precursor. The smooth and/or dome-shaped cross-sectional profile allows for smooth topological transitions without sharp steps, preventing feature discontinuities during deposition and allowing for more complete step coverage of subsequently deposited structures. The inventive profile allows for both the uniform growth of oxide layers by thermal oxidation, and substantially uniform etching rates of the structures. Such oxide layers may have a uniform thickness and provide substantially complete coverage of the underlying electrically active feature. Uniform etching allows for an efficient method of reducing a critical dimension of an electrically active structure by simple isotropic etch.

    Abstract translation: 本发明涉及具有平滑和/或圆顶形轮廓的电介质，导体和/或半导体层的电活性器件（例如，电容器，晶体管，二极管，浮动栅极存储单元等）和形成这种器件的方法 通过沉积或印刷（例如喷墨印刷）包括半导体，金属或电介质前体的油墨组合物。 平滑和/或圆顶形的横截面轮廓允许平滑的拓扑转变而没有尖锐的步骤，防止沉积期间的特征不连续性，并允许随后沉积的结构的更完整的阶梯覆盖。 本发明的轮廓允许通过热氧化均匀生长氧化物层，以及基本均匀的结构蚀刻速率。 这样的氧化物层可以具有均匀的厚度并且提供基本的电活性特征的基本上完整的覆盖。 均匀蚀刻允许通过简单的各向同性蚀刻来降低电活性结构的临界尺寸的有效方法。

    High density memory with storage capacitor
    16.
    发明授权
    High density memory with storage capacitor 有权
    具有存储电容器的高密度存储器

    公开(公告)号：US06586291B1

    公开(公告)日：2003-07-01

    申请号：US10214618

    申请日：2002-08-08

    Applicant: Arvind Kamath ,  Ruggero Castagnetti

    Inventor： Arvind Kamath ,  Ruggero Castagnetti

    IPC: H01L218238

    CPC classification number: H01L27/1087 ,  H01L27/10894 ,  H01L29/66181

    Abstract: A memory cell having a transistor and a capacitor formed in a silicon substrate. The capacitor is formed with a lower electrically conductive plate etched in a projected surface area of the silicon substrate. The lower electrically conductive plate has at least one cross section in the shape of a vee, where the sides of the vee are disposed at an angle of about fifty-five degrees from a top surface of the silicon substrate. The surface area of the lower electrically conductive plate is about seventy-three percent larger than the projected surface area of the silicon substrate in which the lower electrically conductive plate is etched. A capacitor dielectric layer is formed of a first deposited dielectric layer, which is disposed adjacent the lower electrically conductive plate. A top electrically conductive plate is disposed adjacent the capacitor dielectric layer and opposite the lower electrically conductive plate. A transistor is formed having source and drain regions separated by a channel region, and a gate dielectric layer formed of the first deposited dielectric layer.

    Abstract translation: 具有在硅衬底中形成的晶体管和电容器的存储单元。 电容器形成有在硅衬底的投影表面区域中蚀刻的下导电板。 下导电板具有至少一个vee形状的横截面，其中，vee的侧面与硅衬底的顶表面成约五十五度的角度。 下导电板的表面积比其中蚀刻下导电板的硅衬底的投影表面积大约百分之七十三。 电容器介电层由邻近下导电板设置的第一沉积介电层形成。 顶部导电板设置在电容器电介质层附近并与下部导电板相对。 晶体管形成为具有由沟道区域分离的源极和漏极区域以及由第一沉积介电层形成的栅极电介质层。

    Silicon nitride and silicon dioxide gate insulator transistors and method of forming same in a hybrid integrated circuit
    17.
    发明授权
    Silicon nitride and silicon dioxide gate insulator transistors and method of forming same in a hybrid integrated circuit 有权

    公开(公告)号：US06562729B2

    公开(公告)日：2003-05-13

    申请号：US10171700

    申请日：2002-06-14

    Applicant: Arvind Kamath ,  Rajiv Patel ,  Mohammad Mirabedini

    Inventor： Arvind Kamath ,  Rajiv Patel ,  Mohammad Mirabedini

    IPC: H01L2131

    CPC classification number: H01L21/823462

    Abstract: Silicon nitride gate insulators for digital transistors and silicon dioxide gate insulators for analog transistors of a hybrid integrated circuit (IC) are formed in a single integrated fabrication process. A first area of a silicon substrate of the IC is exposed while a second area is initially covered by a silicon dioxide layer. A layer of silicon nitride is formed on the exposed first area while the initial silicon dioxide layer inhibits the formation of silicon nitride on the second area. Thereafter the initial silicon dioxide layer is removed from the second area to allow a new silicon dioxide layer to be formed there from the exposed silicon substrate. The silicon dioxide layer shields against the adverse influences from silicon nitride formation and permits the initial silicon dioxide layer to be removed by etching. The silicon nitride layer shields against the adverse influences of oxidizing new silicon dioxide layer. A slight, beneficial silicon dioxide interface is created between the silicon nitride and the silicon substrate as a result of oxidizing the new layer of silicon dioxide.

    Silicon nitride and silicon dioxide gate insulator transistors and method of forming same in a hybrid integrated circuit
    18.
    发明授权
    Silicon nitride and silicon dioxide gate insulator transistors and method of forming same in a hybrid integrated circuit 有权

    公开(公告)号：US06436845B1

    公开(公告)日：2002-08-20

    申请号：US09723516

    申请日：2000-11-28

    Applicant: Arvind Kamath ,  Rajiv Patel ,  Mohammad Mirabedini

    Inventor： Arvind Kamath ,  Rajiv Patel ,  Mohammad Mirabedini

    IPC: H01L2131

    CPC classification number: H01L21/823462

    Abstract: Silicon nitride gate insulators for digital transistors and silicon dioxide gate insulators for analog transistors of a hybrid integrated circuit (IC) are formed in a single integrated fabrication process. A first area of a silicon substrate of the IC is exposed while a second area is initially covered by a silicon dioxide layer. A layer of silicon nitride is formed on the exposed first area while the initial silicon dioxide layer inhibits the formation of silicon nitride on the second area. Thereafter the initial silicon dioxide layer is removed from the second area to allow a new silicon dioxide layer to be formed there from the exposed silicon substrate. The silicon dioxide layer shields against the adverse influences from silicon nitride formation and permits the initial silicon dioxide layer to be removed by etching. The silicon nitride layer shields against the adverse influences of oxidizing new silicon dioxide layer. A slight, beneficial silicon dioxide interface is created between the silicon nitride and the silicon substrate as a result of oxidizing the new layer of silicon dioxide.

    SOLID-STATE BATTERY AND METHOD OF MAKING THE SAME
    20.
    发明申请
    SOLID-STATE BATTERY AND METHOD OF MAKING THE SAME 有权

    公开(公告)号：US20210320355A1

    公开(公告)日：2021-10-14

    申请号：US17185111

    申请日：2021-02-25

    Applicant: Richard VAN DER LINDE ,  Aditi CHANDRA ,  Mao ITO ,  Alex YAN ,  Arvind KAMATH ,  Shoba RAO ,  Jon SIMMONS

    Inventor： Richard VAN DER LINDE ,  Aditi CHANDRA ,  Mao ITO ,  Alex YAN ,  Arvind KAMATH ,  Shoba RAO ,  Jon SIMMONS

    IPC: H01M50/186 ,  H01M10/058

    Abstract: The present disclosure pertains to a battery and a method of making the same. The battery includes first and second metal substrates, a first solid-state and/or thin-film battery cell on the first metal substrate, a second solid-state and/or thin-film battery cell on the second metal substrate, and a hermetic seal in a peripheral region of the first and second metal substrates. The first and second battery cells are between the first and second metal substrates, and face each other. The method includes respectively forming first and second solid-state and/or thin-film battery cells on first and second metal substrates, placing the second battery cell on the first battery cell so that the first and second battery cells are between the first and second metal substrates, and hermetically sealing the first and second battery cells in a peripheral region of the first and second metal substrates.

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